2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <trace/events/power.h>
33 #include <asm/suspend.h>
34 #include <asm/system_misc.h>
36 #include <plat/sram.h>
37 #include "clockdomain.h"
38 #include "powerdomain.h"
39 #include <plat/sdrc.h>
40 #include <plat/prcm.h>
41 #include <plat/gpmc.h>
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
49 #include "prm2xxx_3xxx.h"
54 /* pm34xx errata defined in pm.h */
58 struct powerdomain *pwrdm;
63 struct list_head node;
66 static LIST_HEAD(pwrst_list);
68 static int (*_omap_save_secure_sram)(u32 *addr);
69 void (*omap3_do_wfi_sram)(void);
71 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
72 static struct powerdomain *core_pwrdm, *per_pwrdm;
74 static void omap3_core_save_context(void)
76 omap3_ctrl_save_padconf();
79 * Force write last pad into memory, as this can fail in some
80 * cases according to errata 1.157, 1.185
82 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
83 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
85 /* Save the Interrupt controller context */
86 omap_intc_save_context();
87 /* Save the GPMC context */
88 omap3_gpmc_save_context();
89 /* Save the system control module context, padconf already save above*/
90 omap3_control_save_context();
91 omap_dma_global_context_save();
94 static void omap3_core_restore_context(void)
96 /* Restore the control module context, padconf restored by h/w */
97 omap3_control_restore_context();
98 /* Restore the GPMC context */
99 omap3_gpmc_restore_context();
100 /* Restore the interrupt controller context */
101 omap_intc_restore_context();
102 omap_dma_global_context_restore();
106 * FIXME: This function should be called before entering off-mode after
107 * OMAP3 secure services have been accessed. Currently it is only called
108 * once during boot sequence, but this works as we are not using secure
111 static void omap3_save_secure_ram_context(void)
114 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
116 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
118 * MPU next state must be set to POWER_ON temporarily,
119 * otherwise the WFI executed inside the ROM code
120 * will hang the system.
122 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
123 ret = _omap_save_secure_sram((u32 *)
124 __pa(omap3_secure_ram_storage));
125 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
126 /* Following is for error tracking, it should not happen */
128 pr_err("save_secure_sram() returns %08x\n", ret);
136 * PRCM Interrupt Handler Helper Function
138 * The purpose of this function is to clear any wake-up events latched
139 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
140 * may occur whilst attempting to clear a PM_WKST_x register and thus
141 * set another bit in this register. A while loop is used to ensure
142 * that any peripheral wake-up events occurring while attempting to
143 * clear the PM_WKST_x are detected and cleared.
145 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
147 u32 wkst, fclk, iclk, clken;
148 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
149 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
150 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
151 u16 grpsel_off = (regs == 3) ?
152 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
155 wkst = omap2_prm_read_mod_reg(module, wkst_off);
156 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
157 wkst &= ~ignore_bits;
159 iclk = omap2_cm_read_mod_reg(module, iclk_off);
160 fclk = omap2_cm_read_mod_reg(module, fclk_off);
163 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
165 * For USBHOST, we don't know whether HOST1 or
166 * HOST2 woke us up, so enable both f-clocks
168 if (module == OMAP3430ES2_USBHOST_MOD)
169 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
170 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
171 omap2_prm_write_mod_reg(wkst, module, wkst_off);
172 wkst = omap2_prm_read_mod_reg(module, wkst_off);
173 wkst &= ~ignore_bits;
176 omap2_cm_write_mod_reg(iclk, module, iclk_off);
177 omap2_cm_write_mod_reg(fclk, module, fclk_off);
183 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
187 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
188 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
190 return c ? IRQ_HANDLED : IRQ_NONE;
193 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
198 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
199 * these are handled in a separate handler to avoid acking
200 * IO events before parsing in mux code
202 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
203 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
204 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
205 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
206 if (omap_rev() > OMAP3430_REV_ES1_0) {
207 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
208 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
211 return c ? IRQ_HANDLED : IRQ_NONE;
214 static void omap34xx_save_context(u32 *save)
218 /* Read Auxiliary Control Register */
219 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
223 /* Read L2 AUX ctrl register */
224 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
229 static int omap34xx_do_sram_idle(unsigned long save_state)
231 omap34xx_cpu_suspend(save_state);
235 void omap_sram_idle(void)
237 /* Variable to tell what needs to be saved and restored
238 * in omap_sram_idle*/
239 /* save_state = 0 => Nothing to save and restored */
240 /* save_state = 1 => Only L1 and logic lost */
241 /* save_state = 2 => Only L2 lost */
242 /* save_state = 3 => L1, L2 and logic lost */
244 int mpu_next_state = PWRDM_POWER_ON;
245 int per_next_state = PWRDM_POWER_ON;
246 int core_next_state = PWRDM_POWER_ON;
251 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
252 switch (mpu_next_state) {
254 case PWRDM_POWER_RET:
255 /* No need to save context */
258 case PWRDM_POWER_OFF:
263 pr_err("Invalid mpu state in sram_idle\n");
268 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
269 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
271 /* Enable IO-PAD and IO-CHAIN wakeups */
272 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
273 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
275 if (mpu_next_state < PWRDM_POWER_ON) {
276 pwrdm_pre_transition(mpu_pwrdm);
277 pwrdm_pre_transition(neon_pwrdm);
281 if (per_next_state < PWRDM_POWER_ON) {
282 pwrdm_pre_transition(per_pwrdm);
283 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
284 omap2_gpio_prepare_for_idle(per_going_off);
288 if (core_next_state < PWRDM_POWER_ON) {
289 pwrdm_pre_transition(core_pwrdm);
290 if (core_next_state == PWRDM_POWER_OFF) {
291 omap3_core_save_context();
292 omap3_cm_save_context();
296 omap3_intc_prepare_idle();
299 * On EMU/HS devices ROM code restores a SRDC value
300 * from scratchpad which has automatic self refresh on timeout
301 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
302 * Hence store/restore the SDRC_POWER register here.
304 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
305 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
306 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
307 core_next_state == PWRDM_POWER_OFF)
308 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
311 * omap3_arm_context is the location where some ARM context
312 * get saved. The rest is placed on the stack, and restored
313 * from there before resuming.
316 omap34xx_save_context(omap3_arm_context);
317 if (save_state == 1 || save_state == 3)
318 cpu_suspend(save_state, omap34xx_do_sram_idle);
320 omap34xx_do_sram_idle(save_state);
322 /* Restore normal SDRC POWER settings */
323 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
324 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
325 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
326 core_next_state == PWRDM_POWER_OFF)
327 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
330 if (core_next_state < PWRDM_POWER_ON) {
331 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
332 if (core_prev_state == PWRDM_POWER_OFF) {
333 omap3_core_restore_context();
334 omap3_cm_restore_context();
335 omap3_sram_restore_context();
336 omap2_sms_restore_context();
338 if (core_next_state == PWRDM_POWER_OFF)
339 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
341 OMAP3_PRM_VOLTCTRL_OFFSET);
342 pwrdm_post_transition(core_pwrdm);
344 omap3_intc_resume_idle();
347 if (per_next_state < PWRDM_POWER_ON) {
348 omap2_gpio_resume_after_idle();
349 pwrdm_post_transition(per_pwrdm);
352 if (mpu_next_state < PWRDM_POWER_ON) {
353 pwrdm_post_transition(mpu_pwrdm);
354 pwrdm_post_transition(neon_pwrdm);
358 static void omap3_pm_idle(void)
362 if (omap_irq_pending())
365 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
366 trace_cpu_idle(1, smp_processor_id());
370 trace_power_end(smp_processor_id());
371 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
377 #ifdef CONFIG_SUSPEND
378 static int omap3_pm_suspend(void)
380 struct power_state *pwrst;
383 /* Read current next_pwrsts */
384 list_for_each_entry(pwrst, &pwrst_list, node)
385 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
386 /* Set ones wanted by suspend */
387 list_for_each_entry(pwrst, &pwrst_list, node) {
388 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
390 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
394 omap3_intc_suspend();
399 /* Restore next_pwrsts */
400 list_for_each_entry(pwrst, &pwrst_list, node) {
401 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
402 if (state > pwrst->next_state) {
403 pr_info("Powerdomain (%s) didn't enter "
405 pwrst->pwrdm->name, pwrst->next_state);
408 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
411 pr_err("Could not enter target state in pm_suspend\n");
413 pr_info("Successfully put all powerdomains to target state\n");
418 #endif /* CONFIG_SUSPEND */
422 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
425 * In cases where IVA2 is activated by bootcode, it may prevent
426 * full-chip retention or off-mode because it is not idle. This
427 * function forces the IVA2 into idle state so it can go
428 * into retention/off and thus allow full-chip retention/off.
431 static void __init omap3_iva_idle(void)
433 /* ensure IVA2 clock is disabled */
434 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
436 /* if no clock activity, nothing else to do */
437 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
438 OMAP3430_CLKACTIVITY_IVA2_MASK))
442 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
443 OMAP3430_RST2_IVA2_MASK |
444 OMAP3430_RST3_IVA2_MASK,
445 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
447 /* Enable IVA2 clock */
448 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
449 OMAP3430_IVA2_MOD, CM_FCLKEN);
451 /* Set IVA2 boot mode to 'idle' */
452 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
453 OMAP343X_CONTROL_IVA2_BOOTMOD);
456 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
458 /* Disable IVA2 clock */
459 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
462 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
463 OMAP3430_RST2_IVA2_MASK |
464 OMAP3430_RST3_IVA2_MASK,
465 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
468 static void __init omap3_d2d_idle(void)
472 /* In a stand alone OMAP3430 where there is not a stacked
473 * modem for the D2D Idle Ack and D2D MStandby must be pulled
474 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
475 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
476 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
477 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
479 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
481 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
483 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
486 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
487 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
488 CORE_MOD, OMAP2_RM_RSTCTRL);
489 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
492 static void __init prcm_setup_regs(void)
494 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
495 OMAP3630_EN_UART4_MASK : 0;
496 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
497 OMAP3630_GRPSEL_UART4_MASK : 0;
499 /* XXX This should be handled by hwmod code or SCM init code */
500 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
503 * Enable control of expternal oscillator through
504 * sys_clkreq. In the long run clock framework should
507 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
508 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
510 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
512 /* setup wakup source */
513 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
514 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
516 /* No need to write EN_IO, that is always enabled */
517 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
518 OMAP3430_GRPSEL_GPT1_MASK |
519 OMAP3430_GRPSEL_GPT12_MASK,
520 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
522 /* Enable PM_WKEN to support DSS LPR */
523 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
524 OMAP3430_DSS_MOD, PM_WKEN);
526 /* Enable wakeups in PER */
527 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
528 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
529 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
530 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
531 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
532 OMAP3430_EN_MCBSP4_MASK,
533 OMAP3430_PER_MOD, PM_WKEN);
534 /* and allow them to wake up MPU */
535 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
536 OMAP3430_GRPSEL_GPIO2_MASK |
537 OMAP3430_GRPSEL_GPIO3_MASK |
538 OMAP3430_GRPSEL_GPIO4_MASK |
539 OMAP3430_GRPSEL_GPIO5_MASK |
540 OMAP3430_GRPSEL_GPIO6_MASK |
541 OMAP3430_GRPSEL_UART3_MASK |
542 OMAP3430_GRPSEL_MCBSP2_MASK |
543 OMAP3430_GRPSEL_MCBSP3_MASK |
544 OMAP3430_GRPSEL_MCBSP4_MASK,
545 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
547 /* Don't attach IVA interrupts */
548 if (omap3_has_iva()) {
549 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
550 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
551 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
552 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
553 OMAP3430_PM_IVAGRPSEL);
556 /* Clear any pending 'reset' flags */
557 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
558 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
559 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
560 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
561 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
562 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
563 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
565 /* Clear any pending PRCM interrupts */
566 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
574 void omap3_pm_off_mode_enable(int enable)
576 struct power_state *pwrst;
580 state = PWRDM_POWER_OFF;
582 state = PWRDM_POWER_RET;
584 list_for_each_entry(pwrst, &pwrst_list, node) {
585 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
586 pwrst->pwrdm == core_pwrdm &&
587 state == PWRDM_POWER_OFF) {
588 pwrst->next_state = PWRDM_POWER_RET;
589 pr_warn("%s: Core OFF disabled due to errata i583\n",
592 pwrst->next_state = state;
594 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
598 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
600 struct power_state *pwrst;
602 list_for_each_entry(pwrst, &pwrst_list, node) {
603 if (pwrst->pwrdm == pwrdm)
604 return pwrst->next_state;
609 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
611 struct power_state *pwrst;
613 list_for_each_entry(pwrst, &pwrst_list, node) {
614 if (pwrst->pwrdm == pwrdm) {
615 pwrst->next_state = state;
622 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
624 struct power_state *pwrst;
629 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
632 pwrst->pwrdm = pwrdm;
633 pwrst->next_state = PWRDM_POWER_RET;
634 list_add(&pwrst->node, &pwrst_list);
636 if (pwrdm_has_hdwr_sar(pwrdm))
637 pwrdm_enable_hdwr_sar(pwrdm);
639 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
643 * Push functions to SRAM
645 * The minimum set of functions is pushed to SRAM for execution:
646 * - omap3_do_wfi for erratum i581 WA,
647 * - save_secure_ram_context for security extensions.
649 void omap_push_sram_idle(void)
651 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
653 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
654 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
655 save_secure_ram_context_sz);
658 static void __init pm_errata_configure(void)
660 if (cpu_is_omap3630()) {
661 pm34xx_errata |= PM_RTA_ERRATUM_i608;
662 /* Enable the l2 cache toggling in sleep logic */
663 enable_omap3630_toggle_l2_on_restore();
664 if (omap_rev() < OMAP3630_REV_ES1_2)
665 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
669 int __init omap3_pm_init(void)
671 struct power_state *pwrst, *tmp;
672 struct clockdomain *neon_clkdm, *mpu_clkdm;
675 if (!omap3_has_io_chain_ctrl())
676 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
678 pm_errata_configure();
680 /* XXX prcm_setup_regs needs to be before enabling hw
681 * supervised mode for powerdomains */
684 ret = request_irq(omap_prcm_event_to_irq("wkup"),
685 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
688 pr_err("pm: Failed to request pm_wkup irq\n");
692 /* IO interrupt is shared with mux code */
693 ret = request_irq(omap_prcm_event_to_irq("io"),
694 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
696 enable_irq(omap_prcm_event_to_irq("io"));
699 pr_err("pm: Failed to request pm_io irq\n");
703 ret = pwrdm_for_each(pwrdms_setup, NULL);
705 pr_err("Failed to setup powerdomains\n");
709 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
711 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
712 if (mpu_pwrdm == NULL) {
713 pr_err("Failed to get mpu_pwrdm\n");
718 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
719 per_pwrdm = pwrdm_lookup("per_pwrdm");
720 core_pwrdm = pwrdm_lookup("core_pwrdm");
722 neon_clkdm = clkdm_lookup("neon_clkdm");
723 mpu_clkdm = clkdm_lookup("mpu_clkdm");
725 #ifdef CONFIG_SUSPEND
726 omap_pm_suspend = omap3_pm_suspend;
729 arm_pm_idle = omap3_pm_idle;
733 * RTA is disabled during initialization as per erratum i608
734 * it is safer to disable RTA by the bootloader, but we would like
735 * to be doubly sure here and prevent any mishaps.
737 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
738 omap3630_ctrl_disable_rta();
740 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
741 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
742 omap3_secure_ram_storage =
743 kmalloc(0x803F, GFP_KERNEL);
744 if (!omap3_secure_ram_storage)
745 pr_err("Memory allocation failed when "
746 "allocating for secure sram context\n");
751 omap_dma_global_context_save();
752 omap3_save_secure_ram_context();
753 omap_dma_global_context_restore();
759 omap3_save_scratchpad_contents();
763 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
764 list_del(&pwrst->node);
767 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
769 free_irq(omap_prcm_event_to_irq("wkup"), NULL);