2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
32 #include <plat/sram.h>
33 #include <plat/clockdomain.h>
34 #include <plat/powerdomain.h>
35 #include <plat/control.h>
36 #include <plat/serial.h>
37 #include <plat/sdrc.h>
38 #include <plat/prcm.h>
39 #include <plat/gpmc.h>
41 #include <plat/dmtimer.h>
43 #include <asm/tlbflush.h>
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
53 /* Scratchpad offsets */
54 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
55 #define OMAP343X_TABLE_VALUE_OFFSET 0x30
56 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
59 struct powerdomain *pwrdm;
64 struct list_head node;
67 static LIST_HEAD(pwrst_list);
69 static void (*_omap_sram_idle)(u32 *addr, int save_state);
71 static int (*_omap_save_secure_sram)(u32 *addr);
73 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
74 static struct powerdomain *core_pwrdm, *per_pwrdm;
75 static struct powerdomain *cam_pwrdm;
77 static inline void omap3_per_save_context(void)
79 omap_gpio_save_context();
82 static inline void omap3_per_restore_context(void)
84 omap_gpio_restore_context();
87 static void omap3_enable_io_chain(void)
91 if (omap_rev() >= OMAP3430_REV_ES3_1) {
92 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
94 /* Do a readback to assure write has been done */
95 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
97 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
98 OMAP3430_ST_IO_CHAIN_MASK)) {
100 if (timeout > 1000) {
101 printk(KERN_ERR "Wake up daisy chain "
102 "activation failed.\n");
105 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
111 static void omap3_disable_io_chain(void)
113 if (omap_rev() >= OMAP3430_REV_ES3_1)
114 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
118 static void omap3_core_save_context(void)
120 u32 control_padconf_off;
122 /* Save the padconf registers */
123 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
124 control_padconf_off |= START_PADCONF_SAVE;
125 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
126 /* wait for the save to complete */
127 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
128 & PADCONF_SAVE_DONE))
132 * Force write last pad into memory, as this can fail in some
133 * cases according to erratas 1.157, 1.185
135 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
136 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
138 /* Save the Interrupt controller context */
139 omap_intc_save_context();
140 /* Save the GPMC context */
141 omap3_gpmc_save_context();
142 /* Save the system control module context, padconf already save above*/
143 omap3_control_save_context();
144 omap_dma_global_context_save();
147 static void omap3_core_restore_context(void)
149 /* Restore the control module context, padconf restored by h/w */
150 omap3_control_restore_context();
151 /* Restore the GPMC context */
152 omap3_gpmc_restore_context();
153 /* Restore the interrupt controller context */
154 omap_intc_restore_context();
155 omap_dma_global_context_restore();
159 * FIXME: This function should be called before entering off-mode after
160 * OMAP3 secure services have been accessed. Currently it is only called
161 * once during boot sequence, but this works as we are not using secure
164 static void omap3_save_secure_ram_context(u32 target_mpu_state)
168 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
170 * MPU next state must be set to POWER_ON temporarily,
171 * otherwise the WFI executed inside the ROM code
172 * will hang the system.
174 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
175 ret = _omap_save_secure_sram((u32 *)
176 __pa(omap3_secure_ram_storage));
177 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
178 /* Following is for error tracking, it should not happen */
180 printk(KERN_ERR "save_secure_sram() returns %08x\n",
189 * PRCM Interrupt Handler Helper Function
191 * The purpose of this function is to clear any wake-up events latched
192 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
193 * may occur whilst attempting to clear a PM_WKST_x register and thus
194 * set another bit in this register. A while loop is used to ensure
195 * that any peripheral wake-up events occurring while attempting to
196 * clear the PM_WKST_x are detected and cleared.
198 static int prcm_clear_mod_irqs(s16 module, u8 regs)
200 u32 wkst, fclk, iclk, clken;
201 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
202 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
203 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
204 u16 grpsel_off = (regs == 3) ?
205 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
208 wkst = prm_read_mod_reg(module, wkst_off);
209 wkst &= prm_read_mod_reg(module, grpsel_off);
211 iclk = cm_read_mod_reg(module, iclk_off);
212 fclk = cm_read_mod_reg(module, fclk_off);
215 cm_set_mod_reg_bits(clken, module, iclk_off);
217 * For USBHOST, we don't know whether HOST1 or
218 * HOST2 woke us up, so enable both f-clocks
220 if (module == OMAP3430ES2_USBHOST_MOD)
221 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
222 cm_set_mod_reg_bits(clken, module, fclk_off);
223 prm_write_mod_reg(wkst, module, wkst_off);
224 wkst = prm_read_mod_reg(module, wkst_off);
227 cm_write_mod_reg(iclk, module, iclk_off);
228 cm_write_mod_reg(fclk, module, fclk_off);
234 static int _prcm_int_handle_wakeup(void)
238 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
239 c += prcm_clear_mod_irqs(CORE_MOD, 1);
240 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
241 if (omap_rev() > OMAP3430_REV_ES1_0) {
242 c += prcm_clear_mod_irqs(CORE_MOD, 3);
243 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
250 * PRCM Interrupt Handler
252 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
253 * interrupts from the PRCM for the MPU. These bits must be cleared in
254 * order to clear the PRCM interrupt. The PRCM interrupt handler is
255 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
256 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
257 * register indicates that a wake-up event is pending for the MPU and
258 * this bit can only be cleared if the all the wake-up events latched
259 * in the various PM_WKST_x registers have been cleared. The interrupt
260 * handler is implemented using a do-while loop so that if a wake-up
261 * event occurred during the processing of the prcm interrupt handler
262 * (setting a bit in the corresponding PM_WKST_x register and thus
263 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
264 * this would be handled.
266 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
268 u32 irqenable_mpu, irqstatus_mpu;
271 irqenable_mpu = prm_read_mod_reg(OCP_MOD,
272 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
273 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
274 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
275 irqstatus_mpu &= irqenable_mpu;
278 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
279 OMAP3430_IO_ST_MASK)) {
280 c = _prcm_int_handle_wakeup();
283 * Is the MPU PRCM interrupt handler racing with the
284 * IVA2 PRCM interrupt handler ?
286 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
287 "but no wakeup sources are marked\n");
289 /* XXX we need to expand our PRCM interrupt handler */
290 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
291 "no code to handle it (%08x)\n", irqstatus_mpu);
294 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
295 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
297 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
298 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
299 irqstatus_mpu &= irqenable_mpu;
301 } while (irqstatus_mpu);
306 static void restore_control_register(u32 val)
308 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
311 /* Function to restore the table entry that was modified for enabling MMU */
312 static void restore_table_entry(void)
314 u32 *scratchpad_address;
315 u32 previous_value, control_reg_value;
318 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
320 /* Get address of entry that was modified */
321 address = (u32 *)__raw_readl(scratchpad_address +
322 OMAP343X_TABLE_ADDRESS_OFFSET);
323 /* Get the previous value which needs to be restored */
324 previous_value = __raw_readl(scratchpad_address +
325 OMAP343X_TABLE_VALUE_OFFSET);
326 address = __va(address);
327 *address = previous_value;
329 control_reg_value = __raw_readl(scratchpad_address
330 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
331 /* This will enable caches and prediction */
332 restore_control_register(control_reg_value);
335 void omap_sram_idle(void)
337 /* Variable to tell what needs to be saved and restored
338 * in omap_sram_idle*/
339 /* save_state = 0 => Nothing to save and restored */
340 /* save_state = 1 => Only L1 and logic lost */
341 /* save_state = 2 => Only L2 lost */
342 /* save_state = 3 => L1, L2 and logic lost */
344 int mpu_next_state = PWRDM_POWER_ON;
345 int per_next_state = PWRDM_POWER_ON;
346 int core_next_state = PWRDM_POWER_ON;
347 int core_prev_state, per_prev_state;
349 int per_state_modified = 0;
351 if (!_omap_sram_idle)
354 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
355 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
356 pwrdm_clear_all_prev_pwrst(core_pwrdm);
357 pwrdm_clear_all_prev_pwrst(per_pwrdm);
359 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
360 switch (mpu_next_state) {
362 case PWRDM_POWER_RET:
363 /* No need to save context */
366 case PWRDM_POWER_OFF:
371 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
374 pwrdm_pre_transition();
377 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
378 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
380 /* Enable IO-PAD and IO-CHAIN wakeups */
381 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
382 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
383 if (omap3_has_io_wakeup() &&
384 (per_next_state < PWRDM_POWER_ON ||
385 core_next_state < PWRDM_POWER_ON)) {
386 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
387 omap3_enable_io_chain();
391 if (per_next_state < PWRDM_POWER_ON) {
392 omap_uart_prepare_idle(2);
393 omap2_gpio_prepare_for_idle(per_next_state);
394 if (per_next_state == PWRDM_POWER_OFF) {
395 if (core_next_state == PWRDM_POWER_ON) {
396 per_next_state = PWRDM_POWER_RET;
397 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
398 per_state_modified = 1;
400 omap3_per_save_context();
404 if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
405 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
408 if (core_next_state < PWRDM_POWER_ON) {
409 omap_uart_prepare_idle(0);
410 omap_uart_prepare_idle(1);
411 if (core_next_state == PWRDM_POWER_OFF) {
412 omap3_core_save_context();
413 omap3_prcm_save_context();
417 omap3_intc_prepare_idle();
420 * On EMU/HS devices ROM code restores a SRDC value
421 * from scratchpad which has automatic self refresh on timeout
422 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
423 * Hence store/restore the SDRC_POWER register here.
425 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
426 omap_type() != OMAP2_DEVICE_TYPE_GP &&
427 core_next_state == PWRDM_POWER_OFF)
428 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
431 * omap3_arm_context is the location where ARM registers
432 * get saved. The restore path then reads from this
433 * location and restores them back.
435 _omap_sram_idle(omap3_arm_context, save_state);
438 /* Restore normal SDRC POWER settings */
439 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
440 omap_type() != OMAP2_DEVICE_TYPE_GP &&
441 core_next_state == PWRDM_POWER_OFF)
442 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
444 /* Restore table entry modified during MMU restoration */
445 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
446 restore_table_entry();
449 if (core_next_state < PWRDM_POWER_ON) {
450 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
451 if (core_prev_state == PWRDM_POWER_OFF) {
452 omap3_core_restore_context();
453 omap3_prcm_restore_context();
454 omap3_sram_restore_context();
455 omap2_sms_restore_context();
457 omap_uart_resume_idle(0);
458 omap_uart_resume_idle(1);
459 if (core_next_state == PWRDM_POWER_OFF)
460 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
462 OMAP3_PRM_VOLTCTRL_OFFSET);
464 omap3_intc_resume_idle();
467 if (per_next_state < PWRDM_POWER_ON) {
468 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
469 omap2_gpio_resume_after_idle();
470 if (per_prev_state == PWRDM_POWER_OFF)
471 omap3_per_restore_context();
472 omap_uart_resume_idle(2);
473 if (per_state_modified)
474 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
477 /* Disable IO-PAD and IO-CHAIN wakeup */
478 if (omap3_has_io_wakeup() &&
479 (per_next_state < PWRDM_POWER_ON ||
480 core_next_state < PWRDM_POWER_ON)) {
481 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
482 omap3_disable_io_chain();
485 pwrdm_post_transition();
487 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
490 int omap3_can_sleep(void)
492 if (!sleep_while_idle)
494 if (!omap_uart_can_sleep())
499 /* This sets pwrdm state (other than mpu & core. Currently only ON &
500 * RET are supported. Function is assuming that clkdm doesn't have
501 * hw_sup mode enabled. */
502 int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
505 int sleep_switch = 0;
508 if (pwrdm == NULL || IS_ERR(pwrdm))
511 while (!(pwrdm->pwrsts & (1 << state))) {
512 if (state == PWRDM_POWER_OFF)
517 cur_state = pwrdm_read_next_pwrst(pwrdm);
518 if (cur_state == state)
521 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
522 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
524 pwrdm_wait_transition(pwrdm);
527 ret = pwrdm_set_next_pwrst(pwrdm, state);
529 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
535 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
536 pwrdm_wait_transition(pwrdm);
537 pwrdm_state_switch(pwrdm);
544 static void omap3_pm_idle(void)
549 if (!omap3_can_sleep())
552 if (omap_irq_pending() || need_resched())
562 #ifdef CONFIG_SUSPEND
563 static suspend_state_t suspend_state;
565 static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
567 u32 tick_rate, cycles;
569 if (!seconds && !milliseconds)
572 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
573 cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
574 omap_dm_timer_stop(gptimer_wakeup);
575 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
577 pr_info("PM: Resume timer in %u.%03u secs"
578 " (%d ticks at %d ticks/sec.)\n",
579 seconds, milliseconds, cycles, tick_rate);
582 static int omap3_pm_prepare(void)
588 static int omap3_pm_suspend(void)
590 struct power_state *pwrst;
593 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
594 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
595 wakeup_timer_milliseconds);
597 /* Read current next_pwrsts */
598 list_for_each_entry(pwrst, &pwrst_list, node)
599 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
600 /* Set ones wanted by suspend */
601 list_for_each_entry(pwrst, &pwrst_list, node) {
602 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
604 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
608 omap_uart_prepare_suspend();
609 omap3_intc_suspend();
614 /* Restore next_pwrsts */
615 list_for_each_entry(pwrst, &pwrst_list, node) {
616 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
617 if (state > pwrst->next_state) {
618 printk(KERN_INFO "Powerdomain (%s) didn't enter "
620 pwrst->pwrdm->name, pwrst->next_state);
623 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
626 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
628 printk(KERN_INFO "Successfully put all powerdomains "
629 "to target state\n");
634 static int omap3_pm_enter(suspend_state_t unused)
638 switch (suspend_state) {
639 case PM_SUSPEND_STANDBY:
641 ret = omap3_pm_suspend();
650 static void omap3_pm_finish(void)
655 /* Hooks to enable / disable UART interrupts during suspend */
656 static int omap3_pm_begin(suspend_state_t state)
658 suspend_state = state;
659 omap_uart_enable_irqs(0);
663 static void omap3_pm_end(void)
665 suspend_state = PM_SUSPEND_ON;
666 omap_uart_enable_irqs(1);
670 static struct platform_suspend_ops omap_pm_ops = {
671 .begin = omap3_pm_begin,
673 .prepare = omap3_pm_prepare,
674 .enter = omap3_pm_enter,
675 .finish = omap3_pm_finish,
676 .valid = suspend_valid_only_mem,
678 #endif /* CONFIG_SUSPEND */
682 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
685 * In cases where IVA2 is activated by bootcode, it may prevent
686 * full-chip retention or off-mode because it is not idle. This
687 * function forces the IVA2 into idle state so it can go
688 * into retention/off and thus allow full-chip retention/off.
691 static void __init omap3_iva_idle(void)
693 /* ensure IVA2 clock is disabled */
694 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
696 /* if no clock activity, nothing else to do */
697 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
698 OMAP3430_CLKACTIVITY_IVA2_MASK))
702 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
703 OMAP3430_RST2_IVA2_MASK |
704 OMAP3430_RST3_IVA2_MASK,
705 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
707 /* Enable IVA2 clock */
708 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
709 OMAP3430_IVA2_MOD, CM_FCLKEN);
711 /* Set IVA2 boot mode to 'idle' */
712 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
713 OMAP343X_CONTROL_IVA2_BOOTMOD);
716 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
718 /* Disable IVA2 clock */
719 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
722 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
723 OMAP3430_RST2_IVA2_MASK |
724 OMAP3430_RST3_IVA2_MASK,
725 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
728 static void __init omap3_d2d_idle(void)
732 /* In a stand alone OMAP3430 where there is not a stacked
733 * modem for the D2D Idle Ack and D2D MStandby must be pulled
734 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
735 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
736 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
737 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
739 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
741 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
743 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
746 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
747 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
748 CORE_MOD, OMAP2_RM_RSTCTRL);
749 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
752 static void __init prcm_setup_regs(void)
754 /* XXX Reset all wkdeps. This should be done when initializing
756 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
757 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
758 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
759 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
760 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
761 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
762 if (omap_rev() > OMAP3430_REV_ES1_0) {
763 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
764 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
766 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
769 * Enable interface clock autoidle for all modules.
770 * Note that in the long run this should be done by clockfw
773 OMAP3430_AUTO_MODEM_MASK |
774 OMAP3430ES2_AUTO_MMC3_MASK |
775 OMAP3430ES2_AUTO_ICR_MASK |
776 OMAP3430_AUTO_AES2_MASK |
777 OMAP3430_AUTO_SHA12_MASK |
778 OMAP3430_AUTO_DES2_MASK |
779 OMAP3430_AUTO_MMC2_MASK |
780 OMAP3430_AUTO_MMC1_MASK |
781 OMAP3430_AUTO_MSPRO_MASK |
782 OMAP3430_AUTO_HDQ_MASK |
783 OMAP3430_AUTO_MCSPI4_MASK |
784 OMAP3430_AUTO_MCSPI3_MASK |
785 OMAP3430_AUTO_MCSPI2_MASK |
786 OMAP3430_AUTO_MCSPI1_MASK |
787 OMAP3430_AUTO_I2C3_MASK |
788 OMAP3430_AUTO_I2C2_MASK |
789 OMAP3430_AUTO_I2C1_MASK |
790 OMAP3430_AUTO_UART2_MASK |
791 OMAP3430_AUTO_UART1_MASK |
792 OMAP3430_AUTO_GPT11_MASK |
793 OMAP3430_AUTO_GPT10_MASK |
794 OMAP3430_AUTO_MCBSP5_MASK |
795 OMAP3430_AUTO_MCBSP1_MASK |
796 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
797 OMAP3430_AUTO_MAILBOXES_MASK |
798 OMAP3430_AUTO_OMAPCTRL_MASK |
799 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
800 OMAP3430_AUTO_HSOTGUSB_MASK |
801 OMAP3430_AUTO_SAD2D_MASK |
802 OMAP3430_AUTO_SSI_MASK,
803 CORE_MOD, CM_AUTOIDLE1);
806 OMAP3430_AUTO_PKA_MASK |
807 OMAP3430_AUTO_AES1_MASK |
808 OMAP3430_AUTO_RNG_MASK |
809 OMAP3430_AUTO_SHA11_MASK |
810 OMAP3430_AUTO_DES1_MASK,
811 CORE_MOD, CM_AUTOIDLE2);
813 if (omap_rev() > OMAP3430_REV_ES1_0) {
815 OMAP3430_AUTO_MAD2D_MASK |
816 OMAP3430ES2_AUTO_USBTLL_MASK,
817 CORE_MOD, CM_AUTOIDLE3);
821 OMAP3430_AUTO_WDT2_MASK |
822 OMAP3430_AUTO_WDT1_MASK |
823 OMAP3430_AUTO_GPIO1_MASK |
824 OMAP3430_AUTO_32KSYNC_MASK |
825 OMAP3430_AUTO_GPT12_MASK |
826 OMAP3430_AUTO_GPT1_MASK,
827 WKUP_MOD, CM_AUTOIDLE);
830 OMAP3430_AUTO_DSS_MASK,
835 OMAP3430_AUTO_CAM_MASK,
840 OMAP3430_AUTO_GPIO6_MASK |
841 OMAP3430_AUTO_GPIO5_MASK |
842 OMAP3430_AUTO_GPIO4_MASK |
843 OMAP3430_AUTO_GPIO3_MASK |
844 OMAP3430_AUTO_GPIO2_MASK |
845 OMAP3430_AUTO_WDT3_MASK |
846 OMAP3430_AUTO_UART3_MASK |
847 OMAP3430_AUTO_GPT9_MASK |
848 OMAP3430_AUTO_GPT8_MASK |
849 OMAP3430_AUTO_GPT7_MASK |
850 OMAP3430_AUTO_GPT6_MASK |
851 OMAP3430_AUTO_GPT5_MASK |
852 OMAP3430_AUTO_GPT4_MASK |
853 OMAP3430_AUTO_GPT3_MASK |
854 OMAP3430_AUTO_GPT2_MASK |
855 OMAP3430_AUTO_MCBSP4_MASK |
856 OMAP3430_AUTO_MCBSP3_MASK |
857 OMAP3430_AUTO_MCBSP2_MASK,
861 if (omap_rev() > OMAP3430_REV_ES1_0) {
863 OMAP3430ES2_AUTO_USBHOST_MASK,
864 OMAP3430ES2_USBHOST_MOD,
868 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
871 * Set all plls to autoidle. This is needed until autoidle is
874 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
875 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
876 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
879 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
880 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
883 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
888 * Enable control of expternal oscillator through
889 * sys_clkreq. In the long run clock framework should
892 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
893 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
895 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
897 /* setup wakup source */
898 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
899 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
901 /* No need to write EN_IO, that is always enabled */
902 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
903 OMAP3430_GRPSEL_GPT1_MASK |
904 OMAP3430_GRPSEL_GPT12_MASK,
905 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
906 /* For some reason IO doesn't generate wakeup event even if
907 * it is selected to mpu wakeup goup */
908 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
909 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
911 /* Enable PM_WKEN to support DSS LPR */
912 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
913 OMAP3430_DSS_MOD, PM_WKEN);
915 /* Enable wakeups in PER */
916 prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
917 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
918 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
919 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
920 OMAP3430_EN_MCBSP4_MASK,
921 OMAP3430_PER_MOD, PM_WKEN);
922 /* and allow them to wake up MPU */
923 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
924 OMAP3430_GRPSEL_GPIO3_MASK |
925 OMAP3430_GRPSEL_GPIO4_MASK |
926 OMAP3430_GRPSEL_GPIO5_MASK |
927 OMAP3430_GRPSEL_GPIO6_MASK |
928 OMAP3430_GRPSEL_UART3_MASK |
929 OMAP3430_GRPSEL_MCBSP2_MASK |
930 OMAP3430_GRPSEL_MCBSP3_MASK |
931 OMAP3430_GRPSEL_MCBSP4_MASK,
932 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
934 /* Don't attach IVA interrupts */
935 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
936 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
937 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
938 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
940 /* Clear any pending 'reset' flags */
941 prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
942 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
943 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
944 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
945 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
946 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
947 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
949 /* Clear any pending PRCM interrupts */
950 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
956 void omap3_pm_off_mode_enable(int enable)
958 struct power_state *pwrst;
962 state = PWRDM_POWER_OFF;
964 state = PWRDM_POWER_RET;
966 #ifdef CONFIG_CPU_IDLE
967 omap3_cpuidle_update_states();
970 list_for_each_entry(pwrst, &pwrst_list, node) {
971 pwrst->next_state = state;
972 set_pwrdm_state(pwrst->pwrdm, state);
976 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
978 struct power_state *pwrst;
980 list_for_each_entry(pwrst, &pwrst_list, node) {
981 if (pwrst->pwrdm == pwrdm)
982 return pwrst->next_state;
987 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
989 struct power_state *pwrst;
991 list_for_each_entry(pwrst, &pwrst_list, node) {
992 if (pwrst->pwrdm == pwrdm) {
993 pwrst->next_state = state;
1000 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
1002 struct power_state *pwrst;
1007 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
1010 pwrst->pwrdm = pwrdm;
1011 pwrst->next_state = PWRDM_POWER_RET;
1012 list_add(&pwrst->node, &pwrst_list);
1014 if (pwrdm_has_hdwr_sar(pwrdm))
1015 pwrdm_enable_hdwr_sar(pwrdm);
1017 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
1021 * Enable hw supervised mode for all clockdomains if it's
1022 * supported. Initiate sleep transition for other clockdomains, if
1025 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
1027 clkdm_clear_all_wkdeps(clkdm);
1028 clkdm_clear_all_sleepdeps(clkdm);
1030 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
1031 omap2_clkdm_allow_idle(clkdm);
1032 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
1033 atomic_read(&clkdm->usecount) == 0)
1034 omap2_clkdm_sleep(clkdm);
1038 void omap_push_sram_idle(void)
1040 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1041 omap34xx_cpu_suspend_sz);
1042 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1043 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1044 save_secure_ram_context_sz);
1047 static int __init omap3_pm_init(void)
1049 struct power_state *pwrst, *tmp;
1050 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
1053 if (!cpu_is_omap34xx())
1056 printk(KERN_ERR "Power Management for TI OMAP3.\n");
1058 /* XXX prcm_setup_regs needs to be before enabling hw
1059 * supervised mode for powerdomains */
1062 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1063 (irq_handler_t)prcm_interrupt_handler,
1064 IRQF_DISABLED, "prcm", NULL);
1066 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1067 INT_34XX_PRCM_MPU_IRQ);
1071 ret = pwrdm_for_each(pwrdms_setup, NULL);
1073 printk(KERN_ERR "Failed to setup powerdomains\n");
1077 (void) clkdm_for_each(clkdms_setup, NULL);
1079 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1080 if (mpu_pwrdm == NULL) {
1081 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1085 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1086 per_pwrdm = pwrdm_lookup("per_pwrdm");
1087 core_pwrdm = pwrdm_lookup("core_pwrdm");
1088 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1090 neon_clkdm = clkdm_lookup("neon_clkdm");
1091 mpu_clkdm = clkdm_lookup("mpu_clkdm");
1092 per_clkdm = clkdm_lookup("per_clkdm");
1093 core_clkdm = clkdm_lookup("core_clkdm");
1095 omap_push_sram_idle();
1096 #ifdef CONFIG_SUSPEND
1097 suspend_set_ops(&omap_pm_ops);
1098 #endif /* CONFIG_SUSPEND */
1100 pm_idle = omap3_pm_idle;
1103 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1104 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1105 omap3_secure_ram_storage =
1106 kmalloc(0x803F, GFP_KERNEL);
1107 if (!omap3_secure_ram_storage)
1108 printk(KERN_ERR "Memory allocation failed when"
1109 "allocating for secure sram context\n");
1111 local_irq_disable();
1112 local_fiq_disable();
1114 omap_dma_global_context_save();
1115 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1116 omap_dma_global_context_restore();
1122 omap3_save_scratchpad_contents();
1126 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1127 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1128 list_del(&pwrst->node);
1134 late_initcall(omap3_pm_init);