2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2005 Texas Instruments, Inc.
9 * Richard Woodruff <r-woodruff2@ti.com>
11 * Based on pm.c for omap1
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/suspend.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/err.h>
24 #include <linux/gpio.h>
26 #include <mach/sram.h>
27 #include <mach/clockdomain.h>
28 #include <mach/powerdomain.h>
29 #include <mach/control.h>
30 #include <mach/serial.h>
33 #include "cm-regbits-34xx.h"
34 #include "prm-regbits-34xx.h"
40 struct powerdomain *pwrdm;
45 struct list_head node;
48 static LIST_HEAD(pwrst_list);
50 static void (*_omap_sram_idle)(u32 *addr, int save_state);
52 static struct powerdomain *mpu_pwrdm;
54 /* PRCM Interrupt Handler for wakeups */
55 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
57 u32 wkst, irqstatus_mpu;
61 wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
63 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
64 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
65 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
66 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
67 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
68 while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
70 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
71 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
75 wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
77 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
78 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
79 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
80 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
81 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
82 while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
84 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
85 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
87 wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
89 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
90 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
91 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
92 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
93 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
94 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
96 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
97 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
101 wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
103 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
104 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
105 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
106 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
107 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
108 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
110 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
111 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
114 if (omap_rev() > OMAP3430_REV_ES1_0) {
116 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
118 iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
120 fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
122 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
124 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
126 prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
128 while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
131 cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
133 cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
138 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
139 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
140 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
141 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
143 while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
149 static void omap_sram_idle(void)
151 /* Variable to tell what needs to be saved and restored
152 * in omap_sram_idle*/
153 /* save_state = 0 => Nothing to save and restored */
154 /* save_state = 1 => Only L1 and logic lost */
155 /* save_state = 2 => Only L2 lost */
156 /* save_state = 3 => L1, L2 and logic lost */
157 int save_state = 0, mpu_next_state;
159 if (!_omap_sram_idle)
162 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
163 switch (mpu_next_state) {
164 case PWRDM_POWER_RET:
165 /* No need to save context */
170 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
173 pwrdm_pre_transition();
175 omap2_gpio_prepare_for_retention();
176 omap_uart_prepare_idle(0);
177 omap_uart_prepare_idle(1);
178 omap_uart_prepare_idle(2);
180 _omap_sram_idle(NULL, save_state);
183 omap_uart_resume_idle(2);
184 omap_uart_resume_idle(1);
185 omap_uart_resume_idle(0);
186 omap2_gpio_resume_after_retention();
188 pwrdm_post_transition();
193 * Check if functional clocks are enabled before entering
194 * sleep. This function could be behind CONFIG_PM_DEBUG
195 * when all drivers are configuring their sysconfig registers
196 * properly and using their clocks properly.
198 static int omap3_fclks_active(void)
200 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
201 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
203 fck_core1 = cm_read_mod_reg(CORE_MOD,
205 if (omap_rev() > OMAP3430_REV_ES1_0) {
206 fck_core3 = cm_read_mod_reg(CORE_MOD,
207 OMAP3430ES2_CM_FCLKEN3);
208 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
210 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
213 fck_sgx = cm_read_mod_reg(GFX_MOD,
214 OMAP3430ES2_CM_FCLKEN3);
215 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
217 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
219 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
222 /* Ignore UART clocks. These are handled by UART core (serial.c) */
223 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
224 fck_per &= ~OMAP3430_EN_UART3;
226 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
227 fck_cam | fck_per | fck_usbhost)
232 static int omap3_can_sleep(void)
234 if (!omap_uart_can_sleep())
236 if (omap3_fclks_active())
241 /* This sets pwrdm state (other than mpu & core. Currently only ON &
242 * RET are supported. Function is assuming that clkdm doesn't have
243 * hw_sup mode enabled. */
244 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
247 int sleep_switch = 0;
250 if (pwrdm == NULL || IS_ERR(pwrdm))
253 while (!(pwrdm->pwrsts & (1 << state))) {
254 if (state == PWRDM_POWER_OFF)
259 cur_state = pwrdm_read_next_pwrst(pwrdm);
260 if (cur_state == state)
263 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
264 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
266 pwrdm_wait_transition(pwrdm);
269 ret = pwrdm_set_next_pwrst(pwrdm, state);
271 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
277 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
278 pwrdm_wait_transition(pwrdm);
279 pwrdm_state_switch(pwrdm);
286 static void omap3_pm_idle(void)
291 if (!omap3_can_sleep())
294 if (omap_irq_pending())
304 #ifdef CONFIG_SUSPEND
305 static suspend_state_t suspend_state;
307 static int omap3_pm_prepare(void)
313 static int omap3_pm_suspend(void)
315 struct power_state *pwrst;
318 /* Read current next_pwrsts */
319 list_for_each_entry(pwrst, &pwrst_list, node)
320 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
321 /* Set ones wanted by suspend */
322 list_for_each_entry(pwrst, &pwrst_list, node) {
323 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
325 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
329 omap_uart_prepare_suspend();
333 /* Restore next_pwrsts */
334 list_for_each_entry(pwrst, &pwrst_list, node) {
335 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
336 if (state > pwrst->next_state) {
337 printk(KERN_INFO "Powerdomain (%s) didn't enter "
339 pwrst->pwrdm->name, pwrst->next_state);
342 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
345 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
347 printk(KERN_INFO "Successfully put all powerdomains "
348 "to target state\n");
353 static int omap3_pm_enter(suspend_state_t unused)
357 switch (suspend_state) {
358 case PM_SUSPEND_STANDBY:
360 ret = omap3_pm_suspend();
369 static void omap3_pm_finish(void)
374 /* Hooks to enable / disable UART interrupts during suspend */
375 static int omap3_pm_begin(suspend_state_t state)
377 suspend_state = state;
378 omap_uart_enable_irqs(0);
382 static void omap3_pm_end(void)
384 suspend_state = PM_SUSPEND_ON;
385 omap_uart_enable_irqs(1);
389 static struct platform_suspend_ops omap_pm_ops = {
390 .begin = omap3_pm_begin,
392 .prepare = omap3_pm_prepare,
393 .enter = omap3_pm_enter,
394 .finish = omap3_pm_finish,
395 .valid = suspend_valid_only_mem,
397 #endif /* CONFIG_SUSPEND */
401 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
404 * In cases where IVA2 is activated by bootcode, it may prevent
405 * full-chip retention or off-mode because it is not idle. This
406 * function forces the IVA2 into idle state so it can go
407 * into retention/off and thus allow full-chip retention/off.
410 static void __init omap3_iva_idle(void)
412 /* ensure IVA2 clock is disabled */
413 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
415 /* if no clock activity, nothing else to do */
416 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
417 OMAP3430_CLKACTIVITY_IVA2_MASK))
421 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
424 OMAP3430_IVA2_MOD, RM_RSTCTRL);
426 /* Enable IVA2 clock */
427 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
428 OMAP3430_IVA2_MOD, CM_FCLKEN);
430 /* Set IVA2 boot mode to 'idle' */
431 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
432 OMAP343X_CONTROL_IVA2_BOOTMOD);
435 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
437 /* Disable IVA2 clock */
438 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
441 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
444 OMAP3430_IVA2_MOD, RM_RSTCTRL);
447 static void __init omap3_d2d_idle(void)
451 /* In a stand alone OMAP3430 where there is not a stacked
452 * modem for the D2D Idle Ack and D2D MStandby must be pulled
453 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
454 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
455 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
456 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
458 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
460 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
462 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
465 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
466 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
467 CORE_MOD, RM_RSTCTRL);
468 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
471 static void __init prcm_setup_regs(void)
473 /* XXX Reset all wkdeps. This should be done when initializing
475 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
476 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
477 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
478 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
479 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
480 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
481 if (omap_rev() > OMAP3430_REV_ES1_0) {
482 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
483 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
485 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
488 * Enable interface clock autoidle for all modules.
489 * Note that in the long run this should be done by clockfw
492 OMAP3430_AUTO_MODEM |
493 OMAP3430ES2_AUTO_MMC3 |
494 OMAP3430ES2_AUTO_ICR |
496 OMAP3430_AUTO_SHA12 |
500 OMAP3430_AUTO_MSPRO |
502 OMAP3430_AUTO_MCSPI4 |
503 OMAP3430_AUTO_MCSPI3 |
504 OMAP3430_AUTO_MCSPI2 |
505 OMAP3430_AUTO_MCSPI1 |
509 OMAP3430_AUTO_UART2 |
510 OMAP3430_AUTO_UART1 |
511 OMAP3430_AUTO_GPT11 |
512 OMAP3430_AUTO_GPT10 |
513 OMAP3430_AUTO_MCBSP5 |
514 OMAP3430_AUTO_MCBSP1 |
515 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
516 OMAP3430_AUTO_MAILBOXES |
517 OMAP3430_AUTO_OMAPCTRL |
518 OMAP3430ES1_AUTO_FSHOSTUSB |
519 OMAP3430_AUTO_HSOTGUSB |
520 OMAP3430_AUTO_SAD2D |
522 CORE_MOD, CM_AUTOIDLE1);
528 OMAP3430_AUTO_SHA11 |
530 CORE_MOD, CM_AUTOIDLE2);
532 if (omap_rev() > OMAP3430_REV_ES1_0) {
534 OMAP3430_AUTO_MAD2D |
535 OMAP3430ES2_AUTO_USBTLL,
536 CORE_MOD, CM_AUTOIDLE3);
542 OMAP3430_AUTO_GPIO1 |
543 OMAP3430_AUTO_32KSYNC |
544 OMAP3430_AUTO_GPT12 |
546 WKUP_MOD, CM_AUTOIDLE);
559 OMAP3430_AUTO_GPIO6 |
560 OMAP3430_AUTO_GPIO5 |
561 OMAP3430_AUTO_GPIO4 |
562 OMAP3430_AUTO_GPIO3 |
563 OMAP3430_AUTO_GPIO2 |
565 OMAP3430_AUTO_UART3 |
574 OMAP3430_AUTO_MCBSP4 |
575 OMAP3430_AUTO_MCBSP3 |
576 OMAP3430_AUTO_MCBSP2,
580 if (omap_rev() > OMAP3430_REV_ES1_0) {
582 OMAP3430ES2_AUTO_USBHOST,
583 OMAP3430ES2_USBHOST_MOD,
588 * Set all plls to autoidle. This is needed until autoidle is
591 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
592 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
593 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
596 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
597 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
600 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
605 * Enable control of expternal oscillator through
606 * sys_clkreq. In the long run clock framework should
609 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
610 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
612 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
614 /* setup wakup source */
615 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
616 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
618 /* No need to write EN_IO, that is always enabled */
619 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
621 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
622 /* For some reason IO doesn't generate wakeup event even if
623 * it is selected to mpu wakeup goup */
624 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
625 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
627 /* Don't attach IVA interrupts */
628 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
629 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
630 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
631 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
633 /* Clear any pending 'reset' flags */
634 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
635 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
636 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
637 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
638 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
639 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
640 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
642 /* Clear any pending PRCM interrupts */
643 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
645 /* Don't attach IVA interrupts */
646 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
647 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
648 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
649 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
651 /* Clear any pending 'reset' flags */
652 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
653 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
654 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
655 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
656 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
657 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
658 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
660 /* Clear any pending PRCM interrupts */
661 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
667 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
669 struct power_state *pwrst;
671 list_for_each_entry(pwrst, &pwrst_list, node) {
672 if (pwrst->pwrdm == pwrdm)
673 return pwrst->next_state;
678 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
680 struct power_state *pwrst;
682 list_for_each_entry(pwrst, &pwrst_list, node) {
683 if (pwrst->pwrdm == pwrdm) {
684 pwrst->next_state = state;
691 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
693 struct power_state *pwrst;
698 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
701 pwrst->pwrdm = pwrdm;
702 pwrst->next_state = PWRDM_POWER_RET;
703 list_add(&pwrst->node, &pwrst_list);
705 if (pwrdm_has_hdwr_sar(pwrdm))
706 pwrdm_enable_hdwr_sar(pwrdm);
708 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
712 * Enable hw supervised mode for all clockdomains if it's
713 * supported. Initiate sleep transition for other clockdomains, if
716 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
718 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
719 omap2_clkdm_allow_idle(clkdm);
720 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
721 atomic_read(&clkdm->usecount) == 0)
722 omap2_clkdm_sleep(clkdm);
726 static int __init omap3_pm_init(void)
728 struct power_state *pwrst, *tmp;
731 if (!cpu_is_omap34xx())
734 printk(KERN_ERR "Power Management for TI OMAP3.\n");
736 /* XXX prcm_setup_regs needs to be before enabling hw
737 * supervised mode for powerdomains */
740 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
741 (irq_handler_t)prcm_interrupt_handler,
742 IRQF_DISABLED, "prcm", NULL);
744 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
745 INT_34XX_PRCM_MPU_IRQ);
749 ret = pwrdm_for_each(pwrdms_setup, NULL);
751 printk(KERN_ERR "Failed to setup powerdomains\n");
755 (void) clkdm_for_each(clkdms_setup, NULL);
757 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
758 if (mpu_pwrdm == NULL) {
759 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
763 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
764 omap34xx_cpu_suspend_sz);
766 #ifdef CONFIG_SUSPEND
767 suspend_set_ops(&omap_pm_ops);
768 #endif /* CONFIG_SUSPEND */
770 pm_idle = omap3_pm_idle;
775 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
776 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
777 list_del(&pwrst->node);
783 late_initcall(omap3_pm_init);