2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
32 #include <plat/sram.h>
33 #include <plat/clockdomain.h>
34 #include <plat/powerdomain.h>
35 #include <plat/control.h>
36 #include <plat/serial.h>
37 #include <plat/sdrc.h>
38 #include <plat/prcm.h>
39 #include <plat/gpmc.h>
42 #include <asm/tlbflush.h>
45 #include "cm-regbits-34xx.h"
46 #include "prm-regbits-34xx.h"
52 /* Scratchpad offsets */
53 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
54 #define OMAP343X_TABLE_VALUE_OFFSET 0x30
55 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
58 struct powerdomain *pwrdm;
63 struct list_head node;
66 static LIST_HEAD(pwrst_list);
68 static void (*_omap_sram_idle)(u32 *addr, int save_state);
70 static int (*_omap_save_secure_sram)(u32 *addr);
72 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
73 static struct powerdomain *core_pwrdm, *per_pwrdm;
74 static struct powerdomain *cam_pwrdm;
76 static inline void omap3_per_save_context(void)
78 omap_gpio_save_context();
81 static inline void omap3_per_restore_context(void)
83 omap_gpio_restore_context();
86 static void omap3_enable_io_chain(void)
90 if (omap_rev() >= OMAP3430_REV_ES3_1) {
91 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
93 /* Do a readback to assure write has been done */
94 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
96 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
97 OMAP3430_ST_IO_CHAIN_MASK)) {
100 printk(KERN_ERR "Wake up daisy chain "
101 "activation failed.\n");
104 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
110 static void omap3_disable_io_chain(void)
112 if (omap_rev() >= OMAP3430_REV_ES3_1)
113 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
117 static void omap3_core_save_context(void)
119 u32 control_padconf_off;
121 /* Save the padconf registers */
122 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
123 control_padconf_off |= START_PADCONF_SAVE;
124 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
125 /* wait for the save to complete */
126 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
127 & PADCONF_SAVE_DONE))
131 * Force write last pad into memory, as this can fail in some
132 * cases according to erratas 1.157, 1.185
134 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
135 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
137 /* Save the Interrupt controller context */
138 omap_intc_save_context();
139 /* Save the GPMC context */
140 omap3_gpmc_save_context();
141 /* Save the system control module context, padconf already save above*/
142 omap3_control_save_context();
143 omap_dma_global_context_save();
146 static void omap3_core_restore_context(void)
148 /* Restore the control module context, padconf restored by h/w */
149 omap3_control_restore_context();
150 /* Restore the GPMC context */
151 omap3_gpmc_restore_context();
152 /* Restore the interrupt controller context */
153 omap_intc_restore_context();
154 omap_dma_global_context_restore();
158 * FIXME: This function should be called before entering off-mode after
159 * OMAP3 secure services have been accessed. Currently it is only called
160 * once during boot sequence, but this works as we are not using secure
163 static void omap3_save_secure_ram_context(u32 target_mpu_state)
167 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
169 * MPU next state must be set to POWER_ON temporarily,
170 * otherwise the WFI executed inside the ROM code
171 * will hang the system.
173 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
174 ret = _omap_save_secure_sram((u32 *)
175 __pa(omap3_secure_ram_storage));
176 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
177 /* Following is for error tracking, it should not happen */
179 printk(KERN_ERR "save_secure_sram() returns %08x\n",
188 * PRCM Interrupt Handler Helper Function
190 * The purpose of this function is to clear any wake-up events latched
191 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
192 * may occur whilst attempting to clear a PM_WKST_x register and thus
193 * set another bit in this register. A while loop is used to ensure
194 * that any peripheral wake-up events occurring while attempting to
195 * clear the PM_WKST_x are detected and cleared.
197 static int prcm_clear_mod_irqs(s16 module, u8 regs)
199 u32 wkst, fclk, iclk, clken;
200 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
201 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
202 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
203 u16 grpsel_off = (regs == 3) ?
204 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
207 wkst = prm_read_mod_reg(module, wkst_off);
208 wkst &= prm_read_mod_reg(module, grpsel_off);
210 iclk = cm_read_mod_reg(module, iclk_off);
211 fclk = cm_read_mod_reg(module, fclk_off);
214 cm_set_mod_reg_bits(clken, module, iclk_off);
216 * For USBHOST, we don't know whether HOST1 or
217 * HOST2 woke us up, so enable both f-clocks
219 if (module == OMAP3430ES2_USBHOST_MOD)
220 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
221 cm_set_mod_reg_bits(clken, module, fclk_off);
222 prm_write_mod_reg(wkst, module, wkst_off);
223 wkst = prm_read_mod_reg(module, wkst_off);
226 cm_write_mod_reg(iclk, module, iclk_off);
227 cm_write_mod_reg(fclk, module, fclk_off);
233 static int _prcm_int_handle_wakeup(void)
237 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
238 c += prcm_clear_mod_irqs(CORE_MOD, 1);
239 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
240 if (omap_rev() > OMAP3430_REV_ES1_0) {
241 c += prcm_clear_mod_irqs(CORE_MOD, 3);
242 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
249 * PRCM Interrupt Handler
251 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
252 * interrupts from the PRCM for the MPU. These bits must be cleared in
253 * order to clear the PRCM interrupt. The PRCM interrupt handler is
254 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
255 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
256 * register indicates that a wake-up event is pending for the MPU and
257 * this bit can only be cleared if the all the wake-up events latched
258 * in the various PM_WKST_x registers have been cleared. The interrupt
259 * handler is implemented using a do-while loop so that if a wake-up
260 * event occurred during the processing of the prcm interrupt handler
261 * (setting a bit in the corresponding PM_WKST_x register and thus
262 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
263 * this would be handled.
265 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
267 u32 irqenable_mpu, irqstatus_mpu;
270 irqenable_mpu = prm_read_mod_reg(OCP_MOD,
271 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
272 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
273 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
274 irqstatus_mpu &= irqenable_mpu;
277 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
278 OMAP3430_IO_ST_MASK)) {
279 c = _prcm_int_handle_wakeup();
282 * Is the MPU PRCM interrupt handler racing with the
283 * IVA2 PRCM interrupt handler ?
285 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
286 "but no wakeup sources are marked\n");
288 /* XXX we need to expand our PRCM interrupt handler */
289 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
290 "no code to handle it (%08x)\n", irqstatus_mpu);
293 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
294 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
296 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
297 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
298 irqstatus_mpu &= irqenable_mpu;
300 } while (irqstatus_mpu);
305 static void restore_control_register(u32 val)
307 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
310 /* Function to restore the table entry that was modified for enabling MMU */
311 static void restore_table_entry(void)
313 u32 *scratchpad_address;
314 u32 previous_value, control_reg_value;
317 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
319 /* Get address of entry that was modified */
320 address = (u32 *)__raw_readl(scratchpad_address +
321 OMAP343X_TABLE_ADDRESS_OFFSET);
322 /* Get the previous value which needs to be restored */
323 previous_value = __raw_readl(scratchpad_address +
324 OMAP343X_TABLE_VALUE_OFFSET);
325 address = __va(address);
326 *address = previous_value;
328 control_reg_value = __raw_readl(scratchpad_address
329 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
330 /* This will enable caches and prediction */
331 restore_control_register(control_reg_value);
334 void omap_sram_idle(void)
336 /* Variable to tell what needs to be saved and restored
337 * in omap_sram_idle*/
338 /* save_state = 0 => Nothing to save and restored */
339 /* save_state = 1 => Only L1 and logic lost */
340 /* save_state = 2 => Only L2 lost */
341 /* save_state = 3 => L1, L2 and logic lost */
343 int mpu_next_state = PWRDM_POWER_ON;
344 int per_next_state = PWRDM_POWER_ON;
345 int core_next_state = PWRDM_POWER_ON;
346 int core_prev_state, per_prev_state;
349 if (!_omap_sram_idle)
352 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
353 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
354 pwrdm_clear_all_prev_pwrst(core_pwrdm);
355 pwrdm_clear_all_prev_pwrst(per_pwrdm);
357 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
358 switch (mpu_next_state) {
360 case PWRDM_POWER_RET:
361 /* No need to save context */
364 case PWRDM_POWER_OFF:
369 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
372 pwrdm_pre_transition();
375 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
376 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
378 /* Enable IO-PAD and IO-CHAIN wakeups */
379 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
380 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
381 if (omap3_has_io_wakeup() &&
382 (per_next_state < PWRDM_POWER_ON ||
383 core_next_state < PWRDM_POWER_ON)) {
384 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
385 omap3_enable_io_chain();
389 if (per_next_state < PWRDM_POWER_ON) {
390 omap_uart_prepare_idle(2);
391 omap2_gpio_prepare_for_idle(per_next_state);
392 if (per_next_state == PWRDM_POWER_OFF)
393 omap3_per_save_context();
397 if (core_next_state < PWRDM_POWER_ON) {
398 omap_uart_prepare_idle(0);
399 omap_uart_prepare_idle(1);
400 if (core_next_state == PWRDM_POWER_OFF) {
401 omap3_core_save_context();
402 omap3_prcm_save_context();
406 omap3_intc_prepare_idle();
409 * On EMU/HS devices ROM code restores a SRDC value
410 * from scratchpad which has automatic self refresh on timeout
411 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
412 * Hence store/restore the SDRC_POWER register here.
414 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
415 omap_type() != OMAP2_DEVICE_TYPE_GP &&
416 core_next_state == PWRDM_POWER_OFF)
417 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
420 * omap3_arm_context is the location where ARM registers
421 * get saved. The restore path then reads from this
422 * location and restores them back.
424 _omap_sram_idle(omap3_arm_context, save_state);
427 /* Restore normal SDRC POWER settings */
428 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
429 omap_type() != OMAP2_DEVICE_TYPE_GP &&
430 core_next_state == PWRDM_POWER_OFF)
431 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
433 /* Restore table entry modified during MMU restoration */
434 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
435 restore_table_entry();
438 if (core_next_state < PWRDM_POWER_ON) {
439 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
440 if (core_prev_state == PWRDM_POWER_OFF) {
441 omap3_core_restore_context();
442 omap3_prcm_restore_context();
443 omap3_sram_restore_context();
444 omap2_sms_restore_context();
446 omap_uart_resume_idle(0);
447 omap_uart_resume_idle(1);
448 if (core_next_state == PWRDM_POWER_OFF)
449 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
451 OMAP3_PRM_VOLTCTRL_OFFSET);
453 omap3_intc_resume_idle();
456 if (per_next_state < PWRDM_POWER_ON) {
457 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
458 omap2_gpio_resume_after_idle();
459 if (per_prev_state == PWRDM_POWER_OFF)
460 omap3_per_restore_context();
461 omap_uart_resume_idle(2);
464 /* Disable IO-PAD and IO-CHAIN wakeup */
465 if (omap3_has_io_wakeup() &&
466 (per_next_state < PWRDM_POWER_ON ||
467 core_next_state < PWRDM_POWER_ON)) {
468 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
469 omap3_disable_io_chain();
472 pwrdm_post_transition();
474 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
477 int omap3_can_sleep(void)
479 if (!sleep_while_idle)
481 if (!omap_uart_can_sleep())
486 static void omap3_pm_idle(void)
491 if (!omap3_can_sleep())
494 if (omap_irq_pending() || need_resched())
504 #ifdef CONFIG_SUSPEND
505 static suspend_state_t suspend_state;
507 static int omap3_pm_prepare(void)
513 static int omap3_pm_suspend(void)
515 struct power_state *pwrst;
518 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
519 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
520 wakeup_timer_milliseconds);
522 /* Read current next_pwrsts */
523 list_for_each_entry(pwrst, &pwrst_list, node)
524 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
525 /* Set ones wanted by suspend */
526 list_for_each_entry(pwrst, &pwrst_list, node) {
527 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
529 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
533 omap_uart_prepare_suspend();
534 omap3_intc_suspend();
539 /* Restore next_pwrsts */
540 list_for_each_entry(pwrst, &pwrst_list, node) {
541 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
542 if (state > pwrst->next_state) {
543 printk(KERN_INFO "Powerdomain (%s) didn't enter "
545 pwrst->pwrdm->name, pwrst->next_state);
548 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
551 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
553 printk(KERN_INFO "Successfully put all powerdomains "
554 "to target state\n");
559 static int omap3_pm_enter(suspend_state_t unused)
563 switch (suspend_state) {
564 case PM_SUSPEND_STANDBY:
566 ret = omap3_pm_suspend();
575 static void omap3_pm_finish(void)
580 /* Hooks to enable / disable UART interrupts during suspend */
581 static int omap3_pm_begin(suspend_state_t state)
583 suspend_state = state;
584 omap_uart_enable_irqs(0);
588 static void omap3_pm_end(void)
590 suspend_state = PM_SUSPEND_ON;
591 omap_uart_enable_irqs(1);
595 static struct platform_suspend_ops omap_pm_ops = {
596 .begin = omap3_pm_begin,
598 .prepare = omap3_pm_prepare,
599 .enter = omap3_pm_enter,
600 .finish = omap3_pm_finish,
601 .valid = suspend_valid_only_mem,
603 #endif /* CONFIG_SUSPEND */
607 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
610 * In cases where IVA2 is activated by bootcode, it may prevent
611 * full-chip retention or off-mode because it is not idle. This
612 * function forces the IVA2 into idle state so it can go
613 * into retention/off and thus allow full-chip retention/off.
616 static void __init omap3_iva_idle(void)
618 /* ensure IVA2 clock is disabled */
619 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
621 /* if no clock activity, nothing else to do */
622 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
623 OMAP3430_CLKACTIVITY_IVA2_MASK))
627 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
628 OMAP3430_RST2_IVA2_MASK |
629 OMAP3430_RST3_IVA2_MASK,
630 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
632 /* Enable IVA2 clock */
633 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
634 OMAP3430_IVA2_MOD, CM_FCLKEN);
636 /* Set IVA2 boot mode to 'idle' */
637 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
638 OMAP343X_CONTROL_IVA2_BOOTMOD);
641 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
643 /* Disable IVA2 clock */
644 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
647 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
648 OMAP3430_RST2_IVA2_MASK |
649 OMAP3430_RST3_IVA2_MASK,
650 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
653 static void __init omap3_d2d_idle(void)
657 /* In a stand alone OMAP3430 where there is not a stacked
658 * modem for the D2D Idle Ack and D2D MStandby must be pulled
659 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
660 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
661 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
662 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
664 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
666 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
668 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
671 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
672 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
673 CORE_MOD, OMAP2_RM_RSTCTRL);
674 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
677 static void __init prcm_setup_regs(void)
679 /* XXX Reset all wkdeps. This should be done when initializing
681 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
682 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
683 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
684 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
685 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
686 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
687 if (omap_rev() > OMAP3430_REV_ES1_0) {
688 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
689 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
691 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
694 * Enable interface clock autoidle for all modules.
695 * Note that in the long run this should be done by clockfw
698 OMAP3430_AUTO_MODEM_MASK |
699 OMAP3430ES2_AUTO_MMC3_MASK |
700 OMAP3430ES2_AUTO_ICR_MASK |
701 OMAP3430_AUTO_AES2_MASK |
702 OMAP3430_AUTO_SHA12_MASK |
703 OMAP3430_AUTO_DES2_MASK |
704 OMAP3430_AUTO_MMC2_MASK |
705 OMAP3430_AUTO_MMC1_MASK |
706 OMAP3430_AUTO_MSPRO_MASK |
707 OMAP3430_AUTO_HDQ_MASK |
708 OMAP3430_AUTO_MCSPI4_MASK |
709 OMAP3430_AUTO_MCSPI3_MASK |
710 OMAP3430_AUTO_MCSPI2_MASK |
711 OMAP3430_AUTO_MCSPI1_MASK |
712 OMAP3430_AUTO_I2C3_MASK |
713 OMAP3430_AUTO_I2C2_MASK |
714 OMAP3430_AUTO_I2C1_MASK |
715 OMAP3430_AUTO_UART2_MASK |
716 OMAP3430_AUTO_UART1_MASK |
717 OMAP3430_AUTO_GPT11_MASK |
718 OMAP3430_AUTO_GPT10_MASK |
719 OMAP3430_AUTO_MCBSP5_MASK |
720 OMAP3430_AUTO_MCBSP1_MASK |
721 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
722 OMAP3430_AUTO_MAILBOXES_MASK |
723 OMAP3430_AUTO_OMAPCTRL_MASK |
724 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
725 OMAP3430_AUTO_HSOTGUSB_MASK |
726 OMAP3430_AUTO_SAD2D_MASK |
727 OMAP3430_AUTO_SSI_MASK,
728 CORE_MOD, CM_AUTOIDLE1);
731 OMAP3430_AUTO_PKA_MASK |
732 OMAP3430_AUTO_AES1_MASK |
733 OMAP3430_AUTO_RNG_MASK |
734 OMAP3430_AUTO_SHA11_MASK |
735 OMAP3430_AUTO_DES1_MASK,
736 CORE_MOD, CM_AUTOIDLE2);
738 if (omap_rev() > OMAP3430_REV_ES1_0) {
740 OMAP3430_AUTO_MAD2D_MASK |
741 OMAP3430ES2_AUTO_USBTLL_MASK,
742 CORE_MOD, CM_AUTOIDLE3);
746 OMAP3430_AUTO_WDT2_MASK |
747 OMAP3430_AUTO_WDT1_MASK |
748 OMAP3430_AUTO_GPIO1_MASK |
749 OMAP3430_AUTO_32KSYNC_MASK |
750 OMAP3430_AUTO_GPT12_MASK |
751 OMAP3430_AUTO_GPT1_MASK,
752 WKUP_MOD, CM_AUTOIDLE);
755 OMAP3430_AUTO_DSS_MASK,
760 OMAP3430_AUTO_CAM_MASK,
765 OMAP3430_AUTO_GPIO6_MASK |
766 OMAP3430_AUTO_GPIO5_MASK |
767 OMAP3430_AUTO_GPIO4_MASK |
768 OMAP3430_AUTO_GPIO3_MASK |
769 OMAP3430_AUTO_GPIO2_MASK |
770 OMAP3430_AUTO_WDT3_MASK |
771 OMAP3430_AUTO_UART3_MASK |
772 OMAP3430_AUTO_GPT9_MASK |
773 OMAP3430_AUTO_GPT8_MASK |
774 OMAP3430_AUTO_GPT7_MASK |
775 OMAP3430_AUTO_GPT6_MASK |
776 OMAP3430_AUTO_GPT5_MASK |
777 OMAP3430_AUTO_GPT4_MASK |
778 OMAP3430_AUTO_GPT3_MASK |
779 OMAP3430_AUTO_GPT2_MASK |
780 OMAP3430_AUTO_MCBSP4_MASK |
781 OMAP3430_AUTO_MCBSP3_MASK |
782 OMAP3430_AUTO_MCBSP2_MASK,
786 if (omap_rev() > OMAP3430_REV_ES1_0) {
788 OMAP3430ES2_AUTO_USBHOST_MASK,
789 OMAP3430ES2_USBHOST_MOD,
793 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
796 * Set all plls to autoidle. This is needed until autoidle is
799 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
800 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
801 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
804 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
805 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
808 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
813 * Enable control of expternal oscillator through
814 * sys_clkreq. In the long run clock framework should
817 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
818 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
820 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
822 /* setup wakup source */
823 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
824 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
826 /* No need to write EN_IO, that is always enabled */
827 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
828 OMAP3430_GRPSEL_GPT1_MASK |
829 OMAP3430_GRPSEL_GPT12_MASK,
830 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
831 /* For some reason IO doesn't generate wakeup event even if
832 * it is selected to mpu wakeup goup */
833 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
834 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
836 /* Enable PM_WKEN to support DSS LPR */
837 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
838 OMAP3430_DSS_MOD, PM_WKEN);
840 /* Enable wakeups in PER */
841 prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
842 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
843 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
844 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
845 OMAP3430_EN_MCBSP4_MASK,
846 OMAP3430_PER_MOD, PM_WKEN);
847 /* and allow them to wake up MPU */
848 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
849 OMAP3430_GRPSEL_GPIO3_MASK |
850 OMAP3430_GRPSEL_GPIO4_MASK |
851 OMAP3430_GRPSEL_GPIO5_MASK |
852 OMAP3430_GRPSEL_GPIO6_MASK |
853 OMAP3430_GRPSEL_UART3_MASK |
854 OMAP3430_GRPSEL_MCBSP2_MASK |
855 OMAP3430_GRPSEL_MCBSP3_MASK |
856 OMAP3430_GRPSEL_MCBSP4_MASK,
857 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
859 /* Don't attach IVA interrupts */
860 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
861 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
862 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
863 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
865 /* Clear any pending 'reset' flags */
866 prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
867 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
868 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
869 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
870 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
871 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
872 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
874 /* Clear any pending PRCM interrupts */
875 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
881 void omap3_pm_off_mode_enable(int enable)
883 struct power_state *pwrst;
887 state = PWRDM_POWER_OFF;
889 state = PWRDM_POWER_RET;
891 #ifdef CONFIG_CPU_IDLE
892 omap3_cpuidle_update_states();
895 list_for_each_entry(pwrst, &pwrst_list, node) {
896 pwrst->next_state = state;
897 omap_set_pwrdm_state(pwrst->pwrdm, state);
901 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
903 struct power_state *pwrst;
905 list_for_each_entry(pwrst, &pwrst_list, node) {
906 if (pwrst->pwrdm == pwrdm)
907 return pwrst->next_state;
912 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
914 struct power_state *pwrst;
916 list_for_each_entry(pwrst, &pwrst_list, node) {
917 if (pwrst->pwrdm == pwrdm) {
918 pwrst->next_state = state;
925 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
927 struct power_state *pwrst;
932 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
935 pwrst->pwrdm = pwrdm;
936 pwrst->next_state = PWRDM_POWER_RET;
937 list_add(&pwrst->node, &pwrst_list);
939 if (pwrdm_has_hdwr_sar(pwrdm))
940 pwrdm_enable_hdwr_sar(pwrdm);
942 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
946 * Enable hw supervised mode for all clockdomains if it's
947 * supported. Initiate sleep transition for other clockdomains, if
950 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
952 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
953 omap2_clkdm_allow_idle(clkdm);
954 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
955 atomic_read(&clkdm->usecount) == 0)
956 omap2_clkdm_sleep(clkdm);
960 void omap_push_sram_idle(void)
962 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
963 omap34xx_cpu_suspend_sz);
964 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
965 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
966 save_secure_ram_context_sz);
969 static int __init omap3_pm_init(void)
971 struct power_state *pwrst, *tmp;
972 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
975 if (!cpu_is_omap34xx())
978 printk(KERN_ERR "Power Management for TI OMAP3.\n");
980 /* XXX prcm_setup_regs needs to be before enabling hw
981 * supervised mode for powerdomains */
984 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
985 (irq_handler_t)prcm_interrupt_handler,
986 IRQF_DISABLED, "prcm", NULL);
988 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
989 INT_34XX_PRCM_MPU_IRQ);
993 ret = pwrdm_for_each(pwrdms_setup, NULL);
995 printk(KERN_ERR "Failed to setup powerdomains\n");
999 (void) clkdm_for_each(clkdms_setup, NULL);
1001 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1002 if (mpu_pwrdm == NULL) {
1003 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1007 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1008 per_pwrdm = pwrdm_lookup("per_pwrdm");
1009 core_pwrdm = pwrdm_lookup("core_pwrdm");
1010 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1012 neon_clkdm = clkdm_lookup("neon_clkdm");
1013 mpu_clkdm = clkdm_lookup("mpu_clkdm");
1014 per_clkdm = clkdm_lookup("per_clkdm");
1015 core_clkdm = clkdm_lookup("core_clkdm");
1017 omap_push_sram_idle();
1018 #ifdef CONFIG_SUSPEND
1019 suspend_set_ops(&omap_pm_ops);
1020 #endif /* CONFIG_SUSPEND */
1022 pm_idle = omap3_pm_idle;
1025 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1026 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1027 omap3_secure_ram_storage =
1028 kmalloc(0x803F, GFP_KERNEL);
1029 if (!omap3_secure_ram_storage)
1030 printk(KERN_ERR "Memory allocation failed when"
1031 "allocating for secure sram context\n");
1033 local_irq_disable();
1034 local_fiq_disable();
1036 omap_dma_global_context_save();
1037 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1038 omap_dma_global_context_restore();
1044 omap3_save_scratchpad_contents();
1048 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1049 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1050 list_del(&pwrst->node);
1056 late_initcall(omap3_pm_init);