2 * OMAP3 powerdomain definitions
4 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
7 * Paul Walmsley, Jouni Högander
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/bug.h>
20 #include "powerdomain.h"
21 #include "powerdomains2xxx_3xxx_data.h"
23 #include "prcm-common.h"
24 #include "prm2xxx_3xxx.h"
25 #include "prm-regbits-34xx.h"
26 #include "cm2xxx_3xxx.h"
27 #include "cm-regbits-34xx.h"
30 * 34XX-specific powerdomains, dependencies
37 static struct powerdomain iva2_pwrdm = {
39 .prcm_offs = OMAP3430_IVA2_MOD,
40 .pwrsts = PWRSTS_OFF_RET_ON,
41 .pwrsts_logic_ret = PWRSTS_OFF_RET,
55 .voltdm = { .name = "mpu_iva" },
58 static struct powerdomain mpu_3xxx_pwrdm = {
61 .pwrsts = PWRSTS_OFF_RET_ON,
62 .pwrsts_logic_ret = PWRSTS_OFF_RET,
63 .flags = PWRDM_HAS_MPU_QUIRK,
71 .voltdm = { .name = "mpu_iva" },
75 * The USBTLL Save-and-Restore mechanism is broken on
76 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
77 * needs to be disabled on these chips.
78 * Refer: 3430 errata ID i459 and 3630 errata ID i579
80 * Note: setting the SAR flag could help for errata ID i478
81 * which applies to 3430 <= ES3.1, but since the SAR feature
82 * is broken, do not use it.
84 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
86 .prcm_offs = CORE_MOD,
87 .pwrsts = PWRSTS_OFF_RET_ON,
88 .pwrsts_logic_ret = PWRSTS_OFF_RET,
91 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
92 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
95 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
96 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
98 .voltdm = { .name = "core" },
101 static struct powerdomain core_3xxx_es3_1_pwrdm = {
102 .name = "core_pwrdm",
103 .prcm_offs = CORE_MOD,
104 .pwrsts = PWRSTS_OFF_RET_ON,
105 .pwrsts_logic_ret = PWRSTS_OFF_RET,
107 * Setting the SAR flag for errata ID i478 which applies
110 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
113 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
114 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
117 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
118 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
120 .voltdm = { .name = "core" },
123 static struct powerdomain dss_pwrdm = {
125 .prcm_offs = OMAP3430_DSS_MOD,
126 .pwrsts = PWRSTS_OFF_RET_ON,
127 .pwrsts_logic_ret = PWRSTS_RET,
130 [0] = PWRSTS_RET, /* MEMRETSTATE */
133 [0] = PWRSTS_ON, /* MEMONSTATE */
135 .voltdm = { .name = "core" },
139 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
140 * possible SGX powerstate, the SGX device itself does not support
143 static struct powerdomain sgx_pwrdm = {
145 .prcm_offs = OMAP3430ES2_SGX_MOD,
146 /* XXX This is accurate for 3430 SGX, but what about GFX? */
147 .pwrsts = PWRSTS_OFF_ON,
148 .pwrsts_logic_ret = PWRSTS_RET,
151 [0] = PWRSTS_RET, /* MEMRETSTATE */
154 [0] = PWRSTS_ON, /* MEMONSTATE */
156 .voltdm = { .name = "core" },
159 static struct powerdomain cam_pwrdm = {
161 .prcm_offs = OMAP3430_CAM_MOD,
162 .pwrsts = PWRSTS_OFF_RET_ON,
163 .pwrsts_logic_ret = PWRSTS_RET,
166 [0] = PWRSTS_RET, /* MEMRETSTATE */
169 [0] = PWRSTS_ON, /* MEMONSTATE */
171 .voltdm = { .name = "core" },
174 static struct powerdomain per_pwrdm = {
176 .prcm_offs = OMAP3430_PER_MOD,
177 .pwrsts = PWRSTS_OFF_RET_ON,
178 .pwrsts_logic_ret = PWRSTS_OFF_RET,
181 [0] = PWRSTS_RET, /* MEMRETSTATE */
184 [0] = PWRSTS_ON, /* MEMONSTATE */
186 .voltdm = { .name = "core" },
189 static struct powerdomain emu_pwrdm = {
191 .prcm_offs = OMAP3430_EMU_MOD,
192 .voltdm = { .name = "core" },
195 static struct powerdomain neon_pwrdm = {
196 .name = "neon_pwrdm",
197 .prcm_offs = OMAP3430_NEON_MOD,
198 .pwrsts = PWRSTS_OFF_RET_ON,
199 .pwrsts_logic_ret = PWRSTS_RET,
200 .voltdm = { .name = "mpu_iva" },
203 static struct powerdomain usbhost_pwrdm = {
204 .name = "usbhost_pwrdm",
205 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
206 .pwrsts = PWRSTS_OFF_RET_ON,
207 .pwrsts_logic_ret = PWRSTS_RET,
209 * REVISIT: Enabling usb host save and restore mechanism seems to
210 * leave the usb host domain permanently in ACTIVE mode after
211 * changing the usb host power domain state from OFF to active once.
214 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
217 [0] = PWRSTS_RET, /* MEMRETSTATE */
220 [0] = PWRSTS_ON, /* MEMONSTATE */
222 .voltdm = { .name = "core" },
225 static struct powerdomain dpll1_pwrdm = {
226 .name = "dpll1_pwrdm",
227 .prcm_offs = MPU_MOD,
228 .voltdm = { .name = "mpu_iva" },
231 static struct powerdomain dpll2_pwrdm = {
232 .name = "dpll2_pwrdm",
233 .prcm_offs = OMAP3430_IVA2_MOD,
234 .voltdm = { .name = "mpu_iva" },
237 static struct powerdomain dpll3_pwrdm = {
238 .name = "dpll3_pwrdm",
239 .prcm_offs = PLL_MOD,
240 .voltdm = { .name = "core" },
243 static struct powerdomain dpll4_pwrdm = {
244 .name = "dpll4_pwrdm",
245 .prcm_offs = PLL_MOD,
246 .voltdm = { .name = "core" },
249 static struct powerdomain dpll5_pwrdm = {
250 .name = "dpll5_pwrdm",
251 .prcm_offs = PLL_MOD,
252 .voltdm = { .name = "core" },
255 /* As powerdomains are added or removed above, this list must also be changed */
256 static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
272 static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
274 &core_3xxx_pre_es3_1_pwrdm,
278 /* also includes 3630ES1.0 */
279 static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
280 &core_3xxx_pre_es3_1_pwrdm,
287 /* also includes 3630ES1.1+ */
288 static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
289 &core_3xxx_es3_1_pwrdm,
296 void __init omap3xxx_powerdomains_init(void)
300 if (!cpu_is_omap34xx())
303 pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
304 pwrdm_register_pwrdms(powerdomains_omap3430_common);
308 if (rev == OMAP3430_REV_ES1_0)
309 pwrdm_register_pwrdms(powerdomains_omap3430es1);
310 else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
311 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
312 pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
313 else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
314 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
315 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
316 pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
318 WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
320 pwrdm_complete_init();