1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2 #define __ARCH_ARM_MACH_OMAP2_PRM_H
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2009 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include "prcm-common.h"
19 #define OMAP2420_PRM_REGADDR(module, reg) \
20 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
21 #define OMAP2430_PRM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
23 #define OMAP34XX_PRM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25 #define OMAP44XX_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
31 * Architecture-specific global PRM registers
32 * Use __raw_{read,write}l() with these registers.
34 * With a few exceptions, these are the register names beginning with
35 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
36 * IRQSTATUS and IRQENABLE bits.)
40 #define OMAP2_PRCM_REVISION_OFFSET 0x0000
41 #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
42 #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
43 #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
45 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
46 #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
47 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
48 #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
50 #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
51 #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
52 #define OMAP2_PRCM_VOLTST_OFFSET 0x0054
53 #define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
54 #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
55 #define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
56 #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
57 #define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
58 #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
59 #define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
60 #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
61 #define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
62 #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
63 #define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
64 #define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
65 #define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
66 #define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
67 #define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
68 #define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
69 #define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
71 #define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
72 #define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
74 #define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
75 #define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
77 #define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
78 #define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
79 #define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
80 #define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
81 #define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
82 #define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
83 #define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
84 #define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
85 #define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
86 #define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
88 #define OMAP3_PRM_REVISION_OFFSET 0x0004
89 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
90 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
91 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
93 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
94 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
95 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
96 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
99 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
100 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
101 #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
102 #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
103 #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
104 #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
105 #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
106 #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
107 #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
108 #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
109 #define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
110 #define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
111 #define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
112 #define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
113 #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
114 #define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
115 #define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
116 #define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
117 #define OMAP3_PRM_RSTTIME_OFFSET 0x0054
118 #define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
119 #define OMAP3_PRM_RSTST_OFFSET 0x0058
120 #define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
121 #define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
122 #define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
123 #define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
124 #define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
125 #define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
126 #define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
127 #define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
128 #define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
129 #define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
130 #define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
131 #define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
132 #define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
133 #define OMAP3_PRM_POLCTRL_OFFSET 0x009c
134 #define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
135 #define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
136 #define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
137 #define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
138 #define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
139 #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
140 #define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
141 #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
142 #define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
143 #define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
144 #define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
145 #define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
146 #define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
147 #define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
148 #define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
149 #define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
150 #define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
151 #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
152 #define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
153 #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
154 #define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
155 #define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
156 #define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
157 #define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
158 #define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
159 #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
160 #define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
162 #define OMAP3_PRM_CLKSEL_OFFSET 0x0040
163 #define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
164 #define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
165 #define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
168 * Module specific PRM registers from PRM_BASE + domain offset
170 * Use prm_{read,write}_mod_reg() with these registers.
172 * With a few exceptions, these are the register names beginning with
173 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
174 * and IRQENABLE bits.)
178 /* Registers appearing on both 24xx and 34xx */
180 #define RM_RSTCTRL 0x0050
181 #define RM_RSTTIME 0x0054
182 #define RM_RSTST 0x0058
184 #define PM_WKEN 0x00a0
185 #define PM_WKEN1 PM_WKEN
186 #define PM_WKST 0x00b0
187 #define PM_WKST1 PM_WKST
188 #define PM_WKDEP 0x00c8
189 #define PM_EVGENCTRL 0x00d4
190 #define PM_EVGENONTIM 0x00d8
191 #define PM_EVGENOFFTIM 0x00dc
192 #define PM_PWSTCTRL 0x00e0
193 #define PM_PWSTST 0x00e4
195 /* Omap2 specific registers */
196 #define OMAP24XX_PM_WKEN2 0x00a4
197 #define OMAP24XX_PM_WKST2 0x00b4
199 #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
200 #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
201 #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
202 #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
204 /* Omap3 specific registers */
205 #define OMAP3430ES2_PM_WKEN3 0x00f0
206 #define OMAP3430ES2_PM_WKST3 0x00b8
208 #define OMAP3430_PM_MPUGRPSEL 0x00a4
209 #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
210 #define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
212 #define OMAP3430_PM_IVAGRPSEL 0x00a8
213 #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
214 #define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
216 #define OMAP3430_PM_PREPWSTST 0x00e8
218 #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
219 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
222 #ifndef __ASSEMBLER__
224 /* Power/reset management domain register get/set */
225 extern u32 prm_read_mod_reg(s16 module, u16 idx);
226 extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
227 extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
229 /* Read-modify-write bits in a PRM register (by domain) */
230 static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
232 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
235 static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
237 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
243 * Bits common to specific registers
245 * The 3430 register and bit names are generally used,
246 * since they tend to make more sense
249 /* PM_EVGENONTIM_MPU */
250 /* Named PM_EVEGENONTIM_MPU on the 24XX */
251 #define OMAP_ONTIMEVAL_SHIFT 0
252 #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
254 /* PM_EVGENOFFTIM_MPU */
255 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
256 #define OMAP_OFFTIMEVAL_SHIFT 0
257 #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
259 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
260 /* Named PRCM_CLKSSETUP on the 24XX */
261 #define OMAP_SETUP_TIME_SHIFT 0
262 #define OMAP_SETUP_TIME_MASK (0xffff << 0)
264 /* PRM_CLKSRC_CTRL */
265 /* Named PRCM_CLKSRC_CTRL on the 24XX */
266 #define OMAP_SYSCLKDIV_SHIFT 6
267 #define OMAP_SYSCLKDIV_MASK (0x3 << 6)
268 #define OMAP_AUTOEXTCLKMODE_SHIFT 3
269 #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
270 #define OMAP_SYSCLKSEL_SHIFT 0
271 #define OMAP_SYSCLKSEL_MASK (0x3 << 0)
273 /* PM_EVGENCTRL_MPU */
274 #define OMAP_OFFLOADMODE_SHIFT 3
275 #define OMAP_OFFLOADMODE_MASK (0x3 << 3)
276 #define OMAP_ONLOADMODE_SHIFT 1
277 #define OMAP_ONLOADMODE_MASK (0x3 << 1)
278 #define OMAP_ENABLE (1 << 0)
281 /* Named RM_RSTTIME_WKUP on the 24xx */
282 #define OMAP_RSTTIME2_SHIFT 8
283 #define OMAP_RSTTIME2_MASK (0x1f << 8)
284 #define OMAP_RSTTIME1_SHIFT 0
285 #define OMAP_RSTTIME1_MASK (0xff << 0)
288 /* Named RM_RSTCTRL_WKUP on the 24xx */
289 /* 2420 calls RST_DPLL3 'RST_DPLL' */
290 #define OMAP_RST_DPLL3 (1 << 2)
291 #define OMAP_RST_GS (1 << 1)
295 * Bits common to module-shared registers
297 * Not all registers of a particular type support all of these bits -
298 * check TRM if you are unsure
302 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
304 * 2430: PM_PWSTST_MDM
306 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
307 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
310 #define OMAP_INTRANSITION (1 << 20)
314 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
316 * 2430: PM_PWSTST_MDM
318 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
319 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
322 #define OMAP_POWERSTATEST_SHIFT 0
323 #define OMAP_POWERSTATEST_MASK (0x3 << 0)
326 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
327 * called 'COREWKUP_RST'
329 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
330 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
332 #define OMAP_COREDOMAINWKUP_RST (1 << 3)
335 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
339 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
341 #define OMAP_DOMAINWKUP_RST (1 << 2)
344 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
345 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
349 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
351 #define OMAP_GLOBALWARM_RST (1 << 1)
352 #define OMAP_GLOBALCOLD_RST (1 << 0)
355 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
356 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
360 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
363 #define OMAP_EN_WKUP_SHIFT 4
364 #define OMAP_EN_WKUP_MASK (1 << 4)
367 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
370 * 2430: PM_PWSTCTRL_MDM
372 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
373 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
376 #define OMAP_LOGICRETSTATE (1 << 2)
379 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
380 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
382 * 2430: PM_PWSTCTRL_MDM shared bits
384 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
385 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
386 * PM_PWSTCTRL_NEON shared bits
388 #define OMAP_POWERSTATE_SHIFT 0
389 #define OMAP_POWERSTATE_MASK (0x3 << 0)