arch/arm/mach-omap2/prm3xxx.c

   1 /*
   2  * OMAP3xxx PRM module functions
   3  *
   4  * Copyright (C) 2010-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20
  21 #include "soc.h"
  22 #include "common.h"
  23 #include "vp.h"
  24 #include "powerdomain.h"
  25 #include "prm3xxx.h"
  26 #include "prm2xxx_3xxx.h"
  27 #include "cm2xxx_3xxx.h"
  28 #include "prm-regbits-34xx.h"
  29 #include "cm3xxx.h"
  30 #include "cm-regbits-34xx.h"
  31 #include "control.h"
  32
  33 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
  34         OMAP_PRCM_IRQ("wkup",   0,      0),
  35         OMAP_PRCM_IRQ("io",     9,      1),
  36 };
  37
  38 static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
  39         .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
  40         .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
  41         .nr_regs                = 1,
  42         .irqs                   = omap3_prcm_irqs,
  43         .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
  44         .irq                    = 11 + OMAP_INTC_START,
  45         .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
  46         .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
  47         .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
  48         .restore_irqen          = &omap3xxx_prm_restore_irqen,
  49         .reconfigure_io_chain   = &omap3xxx_prm_reconfigure_io_chain,
  50 };
  51
  52 /*
  53  * omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware
  54  *   register (which are specific to OMAP3xxx SoCs) to reset source ID
  55  *   bit shifts (which is an OMAP SoC-independent enumeration)
  56  */
  57 static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = {
  58         { OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
  59         { OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
  60         { OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
  61         { OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
  62         { OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
  63         { OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
  64         { OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT,
  65           OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
  66         { OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT,
  67           OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
  68         { OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
  69         { OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT },
  70         { -1, -1 },
  71 };
  72
  73 /* PRM VP */
  74
  75 /*
  76  * struct omap3_vp - OMAP3 VP register access description.
  77  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
  78  */
  79 struct omap3_vp {
  80         u32 tranxdone_status;
  81 };
  82
  83 static struct omap3_vp omap3_vp[] = {
  84         [OMAP3_VP_VDD_MPU_ID] = {
  85                 .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
  86         },
  87         [OMAP3_VP_VDD_CORE_ID] = {
  88                 .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
  89         },
  90 };
  91
  92 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
  93
  94 u32 omap3_prm_vp_check_txdone(u8 vp_id)
  95 {
  96         struct omap3_vp *vp = &omap3_vp[vp_id];
  97         u32 irqstatus;
  98
  99         irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
 100                                            OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 101         return irqstatus & vp->tranxdone_status;
 102 }
 103
 104 void omap3_prm_vp_clear_txdone(u8 vp_id)
 105 {
 106         struct omap3_vp *vp = &omap3_vp[vp_id];
 107
 108         omap2_prm_write_mod_reg(vp->tranxdone_status,
 109                                 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 110 }
 111
 112 u32 omap3_prm_vcvp_read(u8 offset)
 113 {
 114         return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
 115 }
 116
 117 void omap3_prm_vcvp_write(u32 val, u8 offset)
 118 {
 119         omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
 120 }
 121
 122 u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 123 {
 124         return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
 125 }
 126
 127 /**
 128  * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC
 129  *
 130  * Set the DPLL3 reset bit, which should reboot the SoC.  This is the
 131  * recommended way to restart the SoC, considering Errata i520.  No
 132  * return value.
 133  */
 134 void omap3xxx_prm_dpll3_reset(void)
 135 {
 136         omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD,
 137                                    OMAP2_RM_RSTCTRL);
 138         /* OCP barrier */
 139         omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL);
 140 }
 141
 142 /**
 143  * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
 144  * @events: ptr to a u32, preallocated by caller
 145  *
 146  * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
 147  * MPU IRQs, and store the result into the u32 pointed to by @events.
 148  * No return value.
 149  */
 150 void omap3xxx_prm_read_pending_irqs(unsigned long *events)
 151 {
 152         u32 mask, st;
 153
 154         /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
 155         mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 156         st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 157
 158         events[0] = mask & st;
 159 }
 160
 161 /**
 162  * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
 163  *
 164  * Force any buffered writes to the PRM IP block to complete.  Needed
 165  * by the PRM IRQ handler, which reads and writes directly to the IP
 166  * block, to avoid race conditions after acknowledging or clearing IRQ
 167  * bits.  No return value.
 168  */
 169 void omap3xxx_prm_ocp_barrier(void)
 170 {
 171         omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
 172 }
 173
 174 /**
 175  * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
 176  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
 177  *
 178  * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
 179  * must be allocated by the caller.  Intended to be used in the PRM
 180  * interrupt handler suspend callback.  The OCP barrier is needed to
 181  * ensure the write to disable PRM interrupts reaches the PRM before
 182  * returning; otherwise, spurious interrupts might occur.  No return
 183  * value.
 184  */
 185 void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
 186 {
 187         saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
 188                                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 189         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 190
 191         /* OCP barrier */
 192         omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
 193 }
 194
 195 /**
 196  * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
 197  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
 198  *
 199  * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
 200  * to be used in the PRM interrupt handler resume callback to restore
 201  * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
 202  * barrier should be needed here; any pending PRM interrupts will fire
 203  * once the writes reach the PRM.  No return value.
 204  */
 205 void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 206 {
 207         omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
 208                                 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 209 }
 210
 211 /**
 212  * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
 213  * @module: PRM module to clear wakeups from
 214  * @regs: register set to clear, 1 or 3
 215  * @ignore_bits: wakeup status bits to ignore
 216  *
 217  * The purpose of this function is to clear any wake-up events latched
 218  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 219  * may occur whilst attempting to clear a PM_WKST_x register and thus
 220  * set another bit in this register. A while loop is used to ensure
 221  * that any peripheral wake-up events occurring while attempting to
 222  * clear the PM_WKST_x are detected and cleared.
 223  */
 224 int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 225 {
 226         u32 wkst, fclk, iclk, clken;
 227         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 228         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 229         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 230         u16 grpsel_off = (regs == 3) ?
 231                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 232         int c = 0;
 233
 234         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 235         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 236         wkst &= ~ignore_bits;
 237         if (wkst) {
 238                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 239                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 240                 while (wkst) {
 241                         clken = wkst;
 242                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 243                         /*
 244                          * For USBHOST, we don't know whether HOST1 or
 245                          * HOST2 woke us up, so enable both f-clocks
 246                          */
 247                         if (module == OMAP3430ES2_USBHOST_MOD)
 248                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 249                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 250                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 251                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 252                         wkst &= ~ignore_bits;
 253                         c++;
 254                 }
 255                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 256                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 257         }
 258
 259         return c;
 260 }
 261
 262 /**
 263  * omap3_prm_reset_modem - toggle reset signal for modem
 264  *
 265  * Toggles the reset signal to modem IP block. Required to allow
 266  * OMAP3430 without stacked modem to idle properly.
 267  */
 268 void __init omap3_prm_reset_modem(void)
 269 {
 270         omap2_prm_write_mod_reg(
 271                 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 272                 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 273                                 CORE_MOD, OMAP2_RM_RSTCTRL);
 274         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 275 }
 276
 277 /**
 278  * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
 279  *
 280  * Clear any previously-latched I/O wakeup events and ensure that the
 281  * I/O wakeup gates are aligned with the current mux settings.  Works
 282  * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
 283  * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
 284  * return value.
 285  */
 286 void omap3xxx_prm_reconfigure_io_chain(void)
 287 {
 288         int i = 0;
 289
 290         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 291                                    PM_WKEN);
 292
 293         omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
 294                           OMAP3430_ST_IO_CHAIN_MASK,
 295                           MAX_IOPAD_LATCH_TIME, i);
 296         if (i == MAX_IOPAD_LATCH_TIME)
 297                 pr_warn("PRM: I/O chain clock line assertion timed out\n");
 298
 299         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 300                                      PM_WKEN);
 301
 302         omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
 303                                    PM_WKST);
 304
 305         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
 306 }
 307
 308 /**
 309  * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
 310  *
 311  * Activates the I/O wakeup event latches and allows events logged by
 312  * those latches to signal a wakeup event to the PRCM.  For I/O
 313  * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
 314  * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
 315  * No return value.
 316  */
 317 static void __init omap3xxx_prm_enable_io_wakeup(void)
 318 {
 319         if (prm_features & PRM_HAS_IO_WAKEUP)
 320                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 321                                            PM_WKEN);
 322 }
 323
 324 /**
 325  * omap3xxx_prm_read_reset_sources - return the last SoC reset source
 326  *
 327  * Return a u32 representing the last reset sources of the SoC.  The
 328  * returned reset source bits are standardized across OMAP SoCs.
 329  */
 330 static u32 omap3xxx_prm_read_reset_sources(void)
 331 {
 332         struct prm_reset_src_map *p;
 333         u32 r = 0;
 334         u32 v;
 335
 336         v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
 337
 338         p = omap3xxx_prm_reset_src_map;
 339         while (p->reg_shift >= 0 && p->std_shift >= 0) {
 340                 if (v & (1 << p->reg_shift))
 341                         r |= 1 << p->std_shift;
 342                 p++;
 343         }
 344
 345         return r;
 346 }
 347
 348 /**
 349  * omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention
 350  *
 351  * In cases where IVA2 is activated by bootcode, it may prevent
 352  * full-chip retention or off-mode because it is not idle.  This
 353  * function forces the IVA2 into idle state so it can go
 354  * into retention/off and thus allow full-chip retention/off.
 355  */
 356 void omap3xxx_prm_iva_idle(void)
 357 {
 358         /* ensure IVA2 clock is disabled */
 359         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 360
 361         /* if no clock activity, nothing else to do */
 362         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 363               OMAP3430_CLKACTIVITY_IVA2_MASK))
 364                 return;
 365
 366         /* Reset IVA2 */
 367         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 368                                 OMAP3430_RST2_IVA2_MASK |
 369                                 OMAP3430_RST3_IVA2_MASK,
 370                                 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 371
 372         /* Enable IVA2 clock */
 373         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 374                                OMAP3430_IVA2_MOD, CM_FCLKEN);
 375
 376         /* Set IVA2 boot mode to 'idle' */
 377         omap3_ctrl_set_iva_bootmode_idle();
 378
 379         /* Un-reset IVA2 */
 380         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 381
 382         /* Disable IVA2 clock */
 383         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 384
 385         /* Reset IVA2 */
 386         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 387                                 OMAP3430_RST2_IVA2_MASK |
 388                                 OMAP3430_RST3_IVA2_MASK,
 389                                 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 390 }
 391
 392 /**
 393  * omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status
 394  *                                        and clears it if asserted
 395  *
 396  * Checks if cold-reset has occurred and clears the status bit if yes. Returns
 397  * 1 if cold-reset has occurred, 0 otherwise.
 398  */
 399 int omap3xxx_prm_clear_global_cold_reset(void)
 400 {
 401         if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
 402             OMAP3430_GLOBAL_COLD_RST_MASK) {
 403                 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
 404                                            OMAP3430_GR_MOD,
 405                                            OMAP3_PRM_RSTST_OFFSET);
 406                 return 1;
 407         }
 408
 409         return 0;
 410 }
 411
 412 void omap3_prm_save_scratchpad_contents(u32 *ptr)
 413 {
 414         *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
 415                                         OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 416
 417         *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
 418                                         OMAP3_PRM_CLKSEL_OFFSET);
 419 }
 420
 421 /* Powerdomain low-level functions */
 422
 423 static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 424 {
 425         omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
 426                                    (pwrst << OMAP_POWERSTATE_SHIFT),
 427                                    pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
 428         return 0;
 429 }
 430
 431 static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 432 {
 433         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 434                                              OMAP2_PM_PWSTCTRL,
 435                                              OMAP_POWERSTATE_MASK);
 436 }
 437
 438 static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm)
 439 {
 440         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 441                                              OMAP2_PM_PWSTST,
 442                                              OMAP_POWERSTATEST_MASK);
 443 }
 444
 445 /* Applicable only for OMAP3. Not supported on OMAP2 */
 446 static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
 447 {
 448         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 449                                              OMAP3430_PM_PREPWSTST,
 450                                              OMAP3430_LASTPOWERSTATEENTERED_MASK);
 451 }
 452
 453 static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 454 {
 455         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 456                                              OMAP2_PM_PWSTST,
 457                                              OMAP3430_LOGICSTATEST_MASK);
 458 }
 459
 460 static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 461 {
 462         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 463                                              OMAP2_PM_PWSTCTRL,
 464                                              OMAP3430_LOGICSTATEST_MASK);
 465 }
 466
 467 static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 468 {
 469         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 470                                              OMAP3430_PM_PREPWSTST,
 471                                              OMAP3430_LASTLOGICSTATEENTERED_MASK);
 472 }
 473
 474 static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
 475 {
 476         switch (bank) {
 477         case 0:
 478                 return OMAP3430_LASTMEM1STATEENTERED_MASK;
 479         case 1:
 480                 return OMAP3430_LASTMEM2STATEENTERED_MASK;
 481         case 2:
 482                 return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
 483         case 3:
 484                 return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
 485         default:
 486                 WARN_ON(1); /* should never happen */
 487                 return -EEXIST;
 488         }
 489         return 0;
 490 }
 491
 492 static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 493 {
 494         u32 m;
 495
 496         m = omap3_get_mem_bank_lastmemst_mask(bank);
 497
 498         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 499                                 OMAP3430_PM_PREPWSTST, m);
 500 }
 501
 502 static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 503 {
 504         omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
 505         return 0;
 506 }
 507
 508 static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
 509 {
 510         return omap2_prm_rmw_mod_reg_bits(0,
 511                                           1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
 512                                           pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
 513 }
 514
 515 static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 516 {
 517         return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
 518                                           0, pwrdm->prcm_offs,
 519                                           OMAP2_PM_PWSTCTRL);
 520 }
 521
 522 struct pwrdm_ops omap3_pwrdm_operations = {
 523         .pwrdm_set_next_pwrst   = omap3_pwrdm_set_next_pwrst,
 524         .pwrdm_read_next_pwrst  = omap3_pwrdm_read_next_pwrst,
 525         .pwrdm_read_pwrst       = omap3_pwrdm_read_pwrst,
 526         .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
 527         .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
 528         .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
 529         .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
 530         .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
 531         .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
 532         .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
 533         .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
 534         .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
 535         .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
 536         .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
 537         .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
 538         .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
 539         .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
 540 };
 541
 542 /*
 543  *
 544  */
 545
 546 static int omap3xxx_prm_late_init(void);
 547
 548 static struct prm_ll_data omap3xxx_prm_ll_data = {
 549         .read_reset_sources = &omap3xxx_prm_read_reset_sources,
 550         .late_init = &omap3xxx_prm_late_init,
 551 };
 552
 553 int __init omap3xxx_prm_init(void)
 554 {
 555         if (omap3_has_io_wakeup())
 556                 prm_features |= PRM_HAS_IO_WAKEUP;
 557
 558         return prm_register(&omap3xxx_prm_ll_data);
 559 }
 560
 561 static int omap3xxx_prm_late_init(void)
 562 {
 563         int ret;
 564
 565         if (!(prm_features & PRM_HAS_IO_WAKEUP))
 566                 return 0;
 567
 568         omap3xxx_prm_enable_io_wakeup();
 569         ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
 570         if (!ret)
 571                 irq_set_status_flags(omap_prcm_event_to_irq("io"),
 572                                      IRQ_NOAUTOEN);
 573
 574         return ret;
 575 }
 576
 577 static void __exit omap3xxx_prm_exit(void)
 578 {
 579         prm_unregister(&omap3xxx_prm_ll_data);
 580 }
 581 __exitcall(omap3xxx_prm_exit);