2 * SMS/SDRC (SDRAM controller) common code for OMAP2/3
4 * Copyright (C) 2005, 2008 Texas Instruments Inc.
5 * Copyright (C) 2005, 2008 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
30 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
32 void __iomem *omap2_sdrc_base;
33 void __iomem *omap2_sms_base;
35 struct omap2_sms_regs {
39 static struct omap2_sms_regs sms_context;
41 /* SDRC_POWER register bits */
42 #define SDRC_POWER_EXTCLKDIS_SHIFT 3
43 #define SDRC_POWER_PWDENA_SHIFT 2
44 #define SDRC_POWER_PAGEPOLICY_SHIFT 0
47 * omap2_sms_save_context - Save SMS registers
49 * Save SMS registers that need to be restored after off mode.
51 void omap2_sms_save_context(void)
53 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
57 * omap2_sms_restore_context - Restore SMS registers
59 * Restore SMS registers that need to be Restored after off mode.
61 void omap2_sms_restore_context(void)
63 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
67 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
68 * @r: SDRC clock rate (in Hz)
69 * @sdrc_cs0: chip select 0 ram timings **
70 * @sdrc_cs1: chip select 1 ram timings **
72 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
73 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
74 * structs,for a given SDRC clock rate 'r'.
75 * These parameters control various timing delays in the SDRAM controller
76 * that are expressed in terms of the number of SDRC clock cycles to
77 * wait; hence the clock rate dependency.
79 * Supports 2 different timing parameters for both chip selects.
81 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
82 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
83 * as sdrc_init_params_cs_0.
85 * Fills in the struct omap_sdrc_params * for each chip select.
86 * Returns 0 upon success or -1 upon failure.
88 int omap2_sdrc_get_params(unsigned long r,
89 struct omap_sdrc_params **sdrc_cs0,
90 struct omap_sdrc_params **sdrc_cs1)
92 struct omap_sdrc_params *sp0, *sp1;
94 if (!sdrc_init_params_cs0)
97 sp0 = sdrc_init_params_cs0;
98 sp1 = sdrc_init_params_cs1;
100 while (sp0->rate && sp0->rate != r) {
102 if (sdrc_init_params_cs1)
115 void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
117 omap2_sdrc_base = sdrc;
118 omap2_sms_base = sms;
122 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
123 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
124 * Support for 2 chip selects timings
126 * Turn on smart idle modes for SDRAM scheduler and controller.
127 * Program a known-good configuration for the SDRC to deal with buggy
130 void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
131 struct omap_sdrc_params *sdrc_cs1)
135 l = sms_read_reg(SMS_SYSCONFIG);
138 sms_write_reg(l, SMS_SYSCONFIG);
140 l = sdrc_read_reg(SDRC_SYSCONFIG);
143 sdrc_write_reg(l, SDRC_SYSCONFIG);
145 sdrc_init_params_cs0 = sdrc_cs0;
146 sdrc_init_params_cs1 = sdrc_cs1;
148 /* XXX Enable SRFRONIDLEREQ here also? */
150 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
151 * can cause random memory corruption
153 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
154 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
155 sdrc_write_reg(l, SDRC_POWER);
156 omap2_sms_save_context();