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1 /*
2  * arch/arm/mach-omap2/serial.c
3  *
4  * OMAP2 serial support.
5  *
6  * Copyright (C) 2005-2008 Nokia Corporation
7  * Author: Paul Mundt <paul.mundt@nokia.com>
8  *
9  * Major rework for PM support by Kevin Hilman
10  *
11  * Based off of arch/arm/mach-omap/omap1/serial.c
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15  *
16  * This file is subject to the terms and conditions of the GNU General Public
17  * License. See the file "COPYING" in the main directory of this archive
18  * for more details.
19  */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_reg.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/serial_8250.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/console.h>
31
32 #ifdef CONFIG_SERIAL_OMAP
33 #include <plat/omap-serial.h>
34 #endif
35
36 #include <plat/common.h>
37 #include <plat/board.h>
38 #include <plat/clock.h>
39 #include <plat/dma.h>
40 #include <plat/omap_hwmod.h>
41 #include <plat/omap_device.h>
42
43 #include "prm.h"
44 #include "pm.h"
45 #include "cm.h"
46 #include "prm-regbits-34xx.h"
47 #include "control.h"
48
49 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
50 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
51
52 #define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
53 #define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
54
55 /*
56  * NOTE: By default the serial timeout is disabled as it causes lost characters
57  * over the serial ports. This means that the UART clocks will stay on until
58  * disabled via sysfs. This also causes that any deeper omap sleep states are
59  * blocked. 
60  */
61 #define DEFAULT_TIMEOUT 0
62
63 #define MAX_UART_HWMOD_NAME_LEN         16
64
65 struct omap_uart_state {
66         int num;
67         int can_sleep;
68         struct timer_list timer;
69         u32 timeout;
70
71         void __iomem *wk_st;
72         void __iomem *wk_en;
73         u32 wk_mask;
74         u32 padconf;
75         u32 dma_enabled;
76
77         struct clk *ick;
78         struct clk *fck;
79         int clocked;
80
81         int irq;
82         int regshift;
83         int irqflags;
84         void __iomem *membase;
85         resource_size_t mapbase;
86
87         struct list_head node;
88         struct omap_hwmod *oh;
89         struct platform_device *pdev;
90
91         u32 errata;
92 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
93         int context_valid;
94
95         /* Registers to be saved/restored for OFF-mode */
96         u16 dll;
97         u16 dlh;
98         u16 ier;
99         u16 sysc;
100         u16 scr;
101         u16 wer;
102         u16 mcr;
103 #endif
104 };
105
106 static LIST_HEAD(uart_list);
107 static u8 num_uarts;
108
109 /*
110  * Since these idle/enable hooks are used in the idle path itself
111  * which has interrupts disabled, use the non-locking versions of
112  * the hwmod enable/disable functions.
113  */
114 static int uart_idle_hwmod(struct omap_device *od)
115 {
116         _omap_hwmod_idle(od->hwmods[0]);
117
118         return 0;
119 }
120
121 static int uart_enable_hwmod(struct omap_device *od)
122 {
123         _omap_hwmod_enable(od->hwmods[0]);
124
125         return 0;
126 }
127
128 static struct omap_device_pm_latency omap_uart_latency[] = {
129         {
130                 .deactivate_func = uart_idle_hwmod,
131                 .activate_func   = uart_enable_hwmod,
132                 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
133         },
134 };
135
136 static inline unsigned int __serial_read_reg(struct uart_port *up,
137                                              int offset)
138 {
139         offset <<= up->regshift;
140         return (unsigned int)__raw_readb(up->membase + offset);
141 }
142
143 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
144                                            int offset)
145 {
146         offset <<= uart->regshift;
147         return (unsigned int)__raw_readb(uart->membase + offset);
148 }
149
150 static inline void __serial_write_reg(struct uart_port *up, int offset,
151                 int value)
152 {
153         offset <<= up->regshift;
154         __raw_writeb(value, up->membase + offset);
155 }
156
157 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
158                                     int value)
159 {
160         offset <<= uart->regshift;
161         __raw_writeb(value, uart->membase + offset);
162 }
163
164 /*
165  * Internal UARTs need to be initialized for the 8250 autoconfig to work
166  * properly. Note that the TX watermark initialization may not be needed
167  * once the 8250.c watermark handling code is merged.
168  */
169
170 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
171 {
172         serial_write_reg(uart, UART_OMAP_MDR1, 0x07);
173         serial_write_reg(uart, UART_OMAP_SCR, 0x08);
174         serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
175 }
176
177 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
178
179 /*
180  * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
181  * The access to uart register after MDR1 Access
182  * causes UART to corrupt data.
183  *
184  * Need a delay =
185  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
186  * give 10 times as much
187  */
188 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
189                 u8 fcr_val)
190 {
191         u8 timeout = 255;
192
193         serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
194         udelay(2);
195         serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
196                         UART_FCR_CLEAR_RCVR);
197         /*
198          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
199          * TX_FIFO_E bit is 1.
200          */
201         while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
202                                 (UART_LSR_THRE | UART_LSR_DR))) {
203                 timeout--;
204                 if (!timeout) {
205                         /* Should *never* happen. we warn and carry on */
206                         dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
207                         serial_read_reg(uart, UART_LSR));
208                         break;
209                 }
210                 udelay(1);
211         }
212 }
213
214 static void omap_uart_save_context(struct omap_uart_state *uart)
215 {
216         u16 lcr = 0;
217
218         if (!enable_off_mode)
219                 return;
220
221         lcr = serial_read_reg(uart, UART_LCR);
222         serial_write_reg(uart, UART_LCR, 0xBF);
223         uart->dll = serial_read_reg(uart, UART_DLL);
224         uart->dlh = serial_read_reg(uart, UART_DLM);
225         serial_write_reg(uart, UART_LCR, lcr);
226         uart->ier = serial_read_reg(uart, UART_IER);
227         uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
228         uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
229         uart->wer = serial_read_reg(uart, UART_OMAP_WER);
230         serial_write_reg(uart, UART_LCR, 0x80);
231         uart->mcr = serial_read_reg(uart, UART_MCR);
232         serial_write_reg(uart, UART_LCR, lcr);
233
234         uart->context_valid = 1;
235 }
236
237 static void omap_uart_restore_context(struct omap_uart_state *uart)
238 {
239         u16 efr = 0;
240
241         if (!enable_off_mode)
242                 return;
243
244         if (!uart->context_valid)
245                 return;
246
247         uart->context_valid = 0;
248
249         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
250                 omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
251         else
252                 serial_write_reg(uart, UART_OMAP_MDR1, 0x7);
253         serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
254         efr = serial_read_reg(uart, UART_EFR);
255         serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
256         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
257         serial_write_reg(uart, UART_IER, 0x0);
258         serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
259         serial_write_reg(uart, UART_DLL, uart->dll);
260         serial_write_reg(uart, UART_DLM, uart->dlh);
261         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
262         serial_write_reg(uart, UART_IER, uart->ier);
263         serial_write_reg(uart, UART_LCR, 0x80);
264         serial_write_reg(uart, UART_MCR, uart->mcr);
265         serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
266         serial_write_reg(uart, UART_EFR, efr);
267         serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
268         serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
269         serial_write_reg(uart, UART_OMAP_WER, uart->wer);
270         serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
271         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
272                 omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
273         else
274                 /* UART 16x mode */
275                 serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
276 }
277 #else
278 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
279 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
280 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
281
282 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
283 {
284         if (uart->clocked)
285                 return;
286
287         omap_device_enable(uart->pdev);
288         uart->clocked = 1;
289         omap_uart_restore_context(uart);
290 }
291
292 #ifdef CONFIG_PM
293
294 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
295 {
296         if (!uart->clocked)
297                 return;
298
299         omap_uart_save_context(uart);
300         uart->clocked = 0;
301         omap_device_idle(uart->pdev);
302 }
303
304 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
305 {
306         /* Set wake-enable bit */
307         if (uart->wk_en && uart->wk_mask) {
308                 u32 v = __raw_readl(uart->wk_en);
309                 v |= uart->wk_mask;
310                 __raw_writel(v, uart->wk_en);
311         }
312
313         /* Ensure IOPAD wake-enables are set */
314         if (cpu_is_omap34xx() && uart->padconf) {
315                 u16 v = omap_ctrl_readw(uart->padconf);
316                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
317                 omap_ctrl_writew(v, uart->padconf);
318         }
319 }
320
321 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
322 {
323         /* Clear wake-enable bit */
324         if (uart->wk_en && uart->wk_mask) {
325                 u32 v = __raw_readl(uart->wk_en);
326                 v &= ~uart->wk_mask;
327                 __raw_writel(v, uart->wk_en);
328         }
329
330         /* Ensure IOPAD wake-enables are cleared */
331         if (cpu_is_omap34xx() && uart->padconf) {
332                 u16 v = omap_ctrl_readw(uart->padconf);
333                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
334                 omap_ctrl_writew(v, uart->padconf);
335         }
336 }
337
338 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
339                                                int enable)
340 {
341         u8 idlemode;
342
343         if (enable) {
344                 /**
345                  * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
346                  * in Smartidle Mode When Configured for DMA Operations.
347                  */
348                 if (uart->dma_enabled)
349                         idlemode = HWMOD_IDLEMODE_FORCE;
350                 else
351                         idlemode = HWMOD_IDLEMODE_SMART;
352         } else {
353                 idlemode = HWMOD_IDLEMODE_NO;
354         }
355
356         omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
357 }
358
359 static void omap_uart_block_sleep(struct omap_uart_state *uart)
360 {
361         omap_uart_enable_clocks(uart);
362
363         omap_uart_smart_idle_enable(uart, 0);
364         uart->can_sleep = 0;
365         if (uart->timeout)
366                 mod_timer(&uart->timer, jiffies + uart->timeout);
367         else
368                 del_timer(&uart->timer);
369 }
370
371 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
372 {
373         if (device_may_wakeup(&uart->pdev->dev))
374                 omap_uart_enable_wakeup(uart);
375         else
376                 omap_uart_disable_wakeup(uart);
377
378         if (!uart->clocked)
379                 return;
380
381         omap_uart_smart_idle_enable(uart, 1);
382         uart->can_sleep = 1;
383         del_timer(&uart->timer);
384 }
385
386 static void omap_uart_idle_timer(unsigned long data)
387 {
388         struct omap_uart_state *uart = (struct omap_uart_state *)data;
389
390         omap_uart_allow_sleep(uart);
391 }
392
393 void omap_uart_prepare_idle(int num)
394 {
395         struct omap_uart_state *uart;
396
397         list_for_each_entry(uart, &uart_list, node) {
398                 if (num == uart->num && uart->can_sleep) {
399                         omap_uart_disable_clocks(uart);
400                         return;
401                 }
402         }
403 }
404
405 void omap_uart_resume_idle(int num)
406 {
407         struct omap_uart_state *uart;
408
409         list_for_each_entry(uart, &uart_list, node) {
410                 if (num == uart->num && uart->can_sleep) {
411                         omap_uart_enable_clocks(uart);
412
413                         /* Check for IO pad wakeup */
414                         if (cpu_is_omap34xx() && uart->padconf) {
415                                 u16 p = omap_ctrl_readw(uart->padconf);
416
417                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
418                                         omap_uart_block_sleep(uart);
419                         }
420
421                         /* Check for normal UART wakeup */
422                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
423                                 omap_uart_block_sleep(uart);
424                         return;
425                 }
426         }
427 }
428
429 void omap_uart_prepare_suspend(void)
430 {
431         struct omap_uart_state *uart;
432
433         list_for_each_entry(uart, &uart_list, node) {
434                 omap_uart_allow_sleep(uart);
435         }
436 }
437
438 int omap_uart_can_sleep(void)
439 {
440         struct omap_uart_state *uart;
441         int can_sleep = 1;
442
443         list_for_each_entry(uart, &uart_list, node) {
444                 if (!uart->clocked)
445                         continue;
446
447                 if (!uart->can_sleep) {
448                         can_sleep = 0;
449                         continue;
450                 }
451
452                 /* This UART can now safely sleep. */
453                 omap_uart_allow_sleep(uart);
454         }
455
456         return can_sleep;
457 }
458
459 /**
460  * omap_uart_interrupt()
461  *
462  * This handler is used only to detect that *any* UART interrupt has
463  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
464  * any UART interrupt will trigger the inactivity timer so the
465  * UART will not idle or sleep for its timeout period.
466  *
467  **/
468 /* static int first_interrupt; */
469 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
470 {
471         struct omap_uart_state *uart = dev_id;
472
473         omap_uart_block_sleep(uart);
474
475         return IRQ_NONE;
476 }
477
478 static void omap_uart_idle_init(struct omap_uart_state *uart)
479 {
480         int ret;
481
482         uart->can_sleep = 0;
483         uart->timeout = DEFAULT_TIMEOUT;
484         setup_timer(&uart->timer, omap_uart_idle_timer,
485                     (unsigned long) uart);
486         if (uart->timeout)
487                 mod_timer(&uart->timer, jiffies + uart->timeout);
488         omap_uart_smart_idle_enable(uart, 0);
489
490         if (cpu_is_omap34xx()) {
491                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
492                 u32 wk_mask = 0;
493                 u32 padconf = 0;
494
495                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
496                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
497                 switch (uart->num) {
498                 case 0:
499                         wk_mask = OMAP3430_ST_UART1_MASK;
500                         padconf = 0x182;
501                         break;
502                 case 1:
503                         wk_mask = OMAP3430_ST_UART2_MASK;
504                         padconf = 0x17a;
505                         break;
506                 case 2:
507                         wk_mask = OMAP3430_ST_UART3_MASK;
508                         padconf = 0x19e;
509                         break;
510                 case 3:
511                         wk_mask = OMAP3630_ST_UART4_MASK;
512                         padconf = 0x0d2;
513                         break;
514                 }
515                 uart->wk_mask = wk_mask;
516                 uart->padconf = padconf;
517         } else if (cpu_is_omap24xx()) {
518                 u32 wk_mask = 0;
519                 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
520
521                 switch (uart->num) {
522                 case 0:
523                         wk_mask = OMAP24XX_ST_UART1_MASK;
524                         break;
525                 case 1:
526                         wk_mask = OMAP24XX_ST_UART2_MASK;
527                         break;
528                 case 2:
529                         wk_en = OMAP24XX_PM_WKEN2;
530                         wk_st = OMAP24XX_PM_WKST2;
531                         wk_mask = OMAP24XX_ST_UART3_MASK;
532                         break;
533                 }
534                 uart->wk_mask = wk_mask;
535                 if (cpu_is_omap2430()) {
536                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
537                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
538                 } else if (cpu_is_omap2420()) {
539                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
540                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
541                 }
542         } else {
543                 uart->wk_en = NULL;
544                 uart->wk_st = NULL;
545                 uart->wk_mask = 0;
546                 uart->padconf = 0;
547         }
548
549         uart->irqflags |= IRQF_SHARED;
550         ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
551                                    IRQF_SHARED, "serial idle", (void *)uart);
552         WARN_ON(ret);
553 }
554
555 void omap_uart_enable_irqs(int enable)
556 {
557         int ret;
558         struct omap_uart_state *uart;
559
560         list_for_each_entry(uart, &uart_list, node) {
561                 if (enable) {
562                         pm_runtime_put_sync(&uart->pdev->dev);
563                         ret = request_threaded_irq(uart->irq, NULL,
564                                                    omap_uart_interrupt,
565                                                    IRQF_SHARED,
566                                                    "serial idle",
567                                                    (void *)uart);
568                 } else {
569                         pm_runtime_get_noresume(&uart->pdev->dev);
570                         free_irq(uart->irq, (void *)uart);
571                 }
572         }
573 }
574
575 static ssize_t sleep_timeout_show(struct device *dev,
576                                   struct device_attribute *attr,
577                                   char *buf)
578 {
579         struct platform_device *pdev = to_platform_device(dev);
580         struct omap_device *odev = to_omap_device(pdev);
581         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
582
583         return sprintf(buf, "%u\n", uart->timeout / HZ);
584 }
585
586 static ssize_t sleep_timeout_store(struct device *dev,
587                                    struct device_attribute *attr,
588                                    const char *buf, size_t n)
589 {
590         struct platform_device *pdev = to_platform_device(dev);
591         struct omap_device *odev = to_omap_device(pdev);
592         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
593         unsigned int value;
594
595         if (sscanf(buf, "%u", &value) != 1) {
596                 dev_err(dev, "sleep_timeout_store: Invalid value\n");
597                 return -EINVAL;
598         }
599
600         uart->timeout = value * HZ;
601         if (uart->timeout)
602                 mod_timer(&uart->timer, jiffies + uart->timeout);
603         else
604                 /* A zero value means disable timeout feature */
605                 omap_uart_block_sleep(uart);
606
607         return n;
608 }
609
610 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
611                 sleep_timeout_store);
612 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
613 #else
614 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
615 static void omap_uart_block_sleep(struct omap_uart_state *uart)
616 {
617         /* Needed to enable UART clocks when built without CONFIG_PM */
618         omap_uart_enable_clocks(uart);
619 }
620 #define DEV_CREATE_FILE(dev, attr)
621 #endif /* CONFIG_PM */
622
623 #ifndef CONFIG_SERIAL_OMAP
624 /*
625  * Override the default 8250 read handler: mem_serial_in()
626  * Empty RX fifo read causes an abort on omap3630 and omap4
627  * This function makes sure that an empty rx fifo is not read on these silicons
628  * (OMAP1/2/3430 are not affected)
629  */
630 static unsigned int serial_in_override(struct uart_port *up, int offset)
631 {
632         if (UART_RX == offset) {
633                 unsigned int lsr;
634                 lsr = __serial_read_reg(up, UART_LSR);
635                 if (!(lsr & UART_LSR_DR))
636                         return -EPERM;
637         }
638
639         return __serial_read_reg(up, offset);
640 }
641
642 static void serial_out_override(struct uart_port *up, int offset, int value)
643 {
644         unsigned int status, tmout = 10000;
645
646         status = __serial_read_reg(up, UART_LSR);
647         while (!(status & UART_LSR_THRE)) {
648                 /* Wait up to 10ms for the character(s) to be sent. */
649                 if (--tmout == 0)
650                         break;
651                 udelay(1);
652                 status = __serial_read_reg(up, UART_LSR);
653         }
654         __serial_write_reg(up, offset, value);
655 }
656 #endif
657
658 void __init omap_serial_early_init(void)
659 {
660         int i = 0;
661
662         do {
663                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
664                 struct omap_hwmod *oh;
665                 struct omap_uart_state *uart;
666
667                 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
668                          "uart%d", i + 1);
669                 oh = omap_hwmod_lookup(oh_name);
670                 if (!oh)
671                         break;
672
673                 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
674                 if (WARN_ON(!uart))
675                         return;
676
677                 uart->oh = oh;
678                 uart->num = i++;
679                 list_add_tail(&uart->node, &uart_list);
680                 num_uarts++;
681
682                 /*
683                  * NOTE: omap_hwmod_init() has not yet been called,
684                  *       so no hwmod functions will work yet.
685                  */
686
687                 /*
688                  * During UART early init, device need to be probed
689                  * to determine SoC specific init before omap_device
690                  * is ready.  Therefore, don't allow idle here
691                  */
692                 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
693         } while (1);
694 }
695
696 /**
697  * omap_serial_init_port() - initialize single serial port
698  * @port: serial port number (0-3)
699  *
700  * This function initialies serial driver for given @port only.
701  * Platforms can call this function instead of omap_serial_init()
702  * if they don't plan to use all available UARTs as serial ports.
703  *
704  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
705  * use only one of the two.
706  */
707 void __init omap_serial_init_port(int port)
708 {
709         struct omap_uart_state *uart;
710         struct omap_hwmod *oh;
711         struct omap_device *od;
712         void *pdata = NULL;
713         u32 pdata_size = 0;
714         char *name;
715 #ifndef CONFIG_SERIAL_OMAP
716         struct plat_serial8250_port ports[2] = {
717                 {},
718                 {.flags = 0},
719         };
720         struct plat_serial8250_port *p = &ports[0];
721 #else
722         struct omap_uart_port_info omap_up;
723 #endif
724
725         if (WARN_ON(port < 0))
726                 return;
727         if (WARN_ON(port >= num_uarts))
728                 return;
729
730         list_for_each_entry(uart, &uart_list, node)
731                 if (port == uart->num)
732                         break;
733
734         oh = uart->oh;
735         uart->dma_enabled = 0;
736 #ifndef CONFIG_SERIAL_OMAP
737         name = "serial8250";
738
739         /*
740          * !! 8250 driver does not use standard IORESOURCE* It
741          * has it's own custom pdata that can be taken from
742          * the hwmod resource data.  But, this needs to be
743          * done after the build.
744          *
745          * ?? does it have to be done before the register ??
746          * YES, because platform_device_data_add() copies
747          * pdata, it does not use a pointer.
748          */
749         p->flags = UPF_BOOT_AUTOCONF;
750         p->iotype = UPIO_MEM;
751         p->regshift = 2;
752         p->uartclk = OMAP24XX_BASE_BAUD * 16;
753         p->irq = oh->mpu_irqs[0].irq;
754         p->mapbase = oh->slaves[0]->addr->pa_start;
755         p->membase = omap_hwmod_get_mpu_rt_va(oh);
756         p->irqflags = IRQF_SHARED;
757         p->private_data = uart;
758
759         /*
760          * omap44xx: Never read empty UART fifo
761          * omap3xxx: Never read empty UART fifo on UARTs
762          * with IP rev >=0x52
763          */
764         uart->regshift = p->regshift;
765         uart->membase = p->membase;
766         if (cpu_is_omap44xx())
767                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
768         else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
769                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
770                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
771
772         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
773                 p->serial_in = serial_in_override;
774                 p->serial_out = serial_out_override;
775         }
776
777         pdata = &ports[0];
778         pdata_size = 2 * sizeof(struct plat_serial8250_port);
779 #else
780
781         name = DRIVER_NAME;
782
783         omap_up.dma_enabled = uart->dma_enabled;
784         omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
785         omap_up.mapbase = oh->slaves[0]->addr->pa_start;
786         omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
787         omap_up.irqflags = IRQF_SHARED;
788         omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
789
790         pdata = &omap_up;
791         pdata_size = sizeof(struct omap_uart_port_info);
792 #endif
793
794         if (WARN_ON(!oh))
795                 return;
796
797         od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
798                                omap_uart_latency,
799                                ARRAY_SIZE(omap_uart_latency), false);
800         WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
801              name, oh->name);
802
803         uart->irq = oh->mpu_irqs[0].irq;
804         uart->regshift = 2;
805         uart->mapbase = oh->slaves[0]->addr->pa_start;
806         uart->membase = omap_hwmod_get_mpu_rt_va(oh);
807         uart->pdev = &od->pdev;
808
809         oh->dev_attr = uart;
810
811         acquire_console_sem(); /* in case the earlycon is on the UART */
812
813         /*
814          * Because of early UART probing, UART did not get idled
815          * on init.  Now that omap_device is ready, ensure full idle
816          * before doing omap_device_enable().
817          */
818         omap_hwmod_idle(uart->oh);
819
820         omap_device_enable(uart->pdev);
821         omap_uart_idle_init(uart);
822         omap_uart_reset(uart);
823         omap_hwmod_enable_wakeup(uart->oh);
824         omap_device_idle(uart->pdev);
825
826         /*
827          * Need to block sleep long enough for interrupt driven
828          * driver to start.  Console driver is in polling mode
829          * so device needs to be kept enabled while polling driver
830          * is in use.
831          */
832         if (uart->timeout)
833                 uart->timeout = (30 * HZ);
834         omap_uart_block_sleep(uart);
835         uart->timeout = DEFAULT_TIMEOUT;
836
837         release_console_sem();
838
839         if ((cpu_is_omap34xx() && uart->padconf) ||
840             (uart->wk_en && uart->wk_mask)) {
841                 device_init_wakeup(&od->pdev.dev, true);
842                 DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
843         }
844
845         /* Enable the MDR1 errata for OMAP3 */
846         if (cpu_is_omap34xx())
847                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
848 }
849
850 /**
851  * omap_serial_init() - initialize all supported serial ports
852  *
853  * Initializes all available UARTs as serial ports. Platforms
854  * can call this function when they want to have default behaviour
855  * for serial ports (e.g initialize them all as serial ports).
856  */
857 void __init omap_serial_init(void)
858 {
859         struct omap_uart_state *uart;
860
861         list_for_each_entry(uart, &uart_list, node)
862                 omap_serial_init_port(uart->num);
863 }