2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_reg.h>
23 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/serial_8250.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/console.h>
32 #ifdef CONFIG_SERIAL_OMAP
33 #include <plat/omap-serial.h>
36 #include <plat/common.h>
37 #include <plat/board.h>
38 #include <plat/clock.h>
40 #include <plat/omap_hwmod.h>
41 #include <plat/omap_device.h>
46 #include "prm-regbits-34xx.h"
49 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
50 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
52 #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
53 #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
56 * NOTE: By default the serial timeout is disabled as it causes lost characters
57 * over the serial ports. This means that the UART clocks will stay on until
58 * disabled via sysfs. This also causes that any deeper omap sleep states are
61 #define DEFAULT_TIMEOUT 0
63 #define MAX_UART_HWMOD_NAME_LEN 16
65 struct omap_uart_state {
68 struct timer_list timer;
84 void __iomem *membase;
85 resource_size_t mapbase;
87 struct list_head node;
88 struct omap_hwmod *oh;
89 struct platform_device *pdev;
92 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
95 /* Registers to be saved/restored for OFF-mode */
106 static LIST_HEAD(uart_list);
110 * Since these idle/enable hooks are used in the idle path itself
111 * which has interrupts disabled, use the non-locking versions of
112 * the hwmod enable/disable functions.
114 static int uart_idle_hwmod(struct omap_device *od)
116 _omap_hwmod_idle(od->hwmods[0]);
121 static int uart_enable_hwmod(struct omap_device *od)
123 _omap_hwmod_enable(od->hwmods[0]);
128 static struct omap_device_pm_latency omap_uart_latency[] = {
130 .deactivate_func = uart_idle_hwmod,
131 .activate_func = uart_enable_hwmod,
132 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
136 static inline unsigned int __serial_read_reg(struct uart_port *up,
139 offset <<= up->regshift;
140 return (unsigned int)__raw_readb(up->membase + offset);
143 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
146 offset <<= uart->regshift;
147 return (unsigned int)__raw_readb(uart->membase + offset);
150 static inline void __serial_write_reg(struct uart_port *up, int offset,
153 offset <<= up->regshift;
154 __raw_writeb(value, up->membase + offset);
157 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
160 offset <<= uart->regshift;
161 __raw_writeb(value, uart->membase + offset);
165 * Internal UARTs need to be initialized for the 8250 autoconfig to work
166 * properly. Note that the TX watermark initialization may not be needed
167 * once the 8250.c watermark handling code is merged.
170 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
172 serial_write_reg(uart, UART_OMAP_MDR1, 0x07);
173 serial_write_reg(uart, UART_OMAP_SCR, 0x08);
174 serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
177 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
180 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
181 * The access to uart register after MDR1 Access
182 * causes UART to corrupt data.
185 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
186 * give 10 times as much
188 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
193 serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
195 serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
196 UART_FCR_CLEAR_RCVR);
198 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
199 * TX_FIFO_E bit is 1.
201 while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
202 (UART_LSR_THRE | UART_LSR_DR))) {
205 /* Should *never* happen. we warn and carry on */
206 dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
207 serial_read_reg(uart, UART_LSR));
214 static void omap_uart_save_context(struct omap_uart_state *uart)
218 if (!enable_off_mode)
221 lcr = serial_read_reg(uart, UART_LCR);
222 serial_write_reg(uart, UART_LCR, 0xBF);
223 uart->dll = serial_read_reg(uart, UART_DLL);
224 uart->dlh = serial_read_reg(uart, UART_DLM);
225 serial_write_reg(uart, UART_LCR, lcr);
226 uart->ier = serial_read_reg(uart, UART_IER);
227 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
228 uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
229 uart->wer = serial_read_reg(uart, UART_OMAP_WER);
230 serial_write_reg(uart, UART_LCR, 0x80);
231 uart->mcr = serial_read_reg(uart, UART_MCR);
232 serial_write_reg(uart, UART_LCR, lcr);
234 uart->context_valid = 1;
237 static void omap_uart_restore_context(struct omap_uart_state *uart)
241 if (!enable_off_mode)
244 if (!uart->context_valid)
247 uart->context_valid = 0;
249 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
250 omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
252 serial_write_reg(uart, UART_OMAP_MDR1, 0x7);
253 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
254 efr = serial_read_reg(uart, UART_EFR);
255 serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
256 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
257 serial_write_reg(uart, UART_IER, 0x0);
258 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
259 serial_write_reg(uart, UART_DLL, uart->dll);
260 serial_write_reg(uart, UART_DLM, uart->dlh);
261 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
262 serial_write_reg(uart, UART_IER, uart->ier);
263 serial_write_reg(uart, UART_LCR, 0x80);
264 serial_write_reg(uart, UART_MCR, uart->mcr);
265 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
266 serial_write_reg(uart, UART_EFR, efr);
267 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
268 serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
269 serial_write_reg(uart, UART_OMAP_WER, uart->wer);
270 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
271 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
272 omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
275 serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
278 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
279 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
280 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
282 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
287 omap_device_enable(uart->pdev);
289 omap_uart_restore_context(uart);
294 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
299 omap_uart_save_context(uart);
301 omap_device_idle(uart->pdev);
304 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
306 /* Set wake-enable bit */
307 if (uart->wk_en && uart->wk_mask) {
308 u32 v = __raw_readl(uart->wk_en);
310 __raw_writel(v, uart->wk_en);
313 /* Ensure IOPAD wake-enables are set */
314 if (cpu_is_omap34xx() && uart->padconf) {
315 u16 v = omap_ctrl_readw(uart->padconf);
316 v |= OMAP3_PADCONF_WAKEUPENABLE0;
317 omap_ctrl_writew(v, uart->padconf);
321 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
323 /* Clear wake-enable bit */
324 if (uart->wk_en && uart->wk_mask) {
325 u32 v = __raw_readl(uart->wk_en);
327 __raw_writel(v, uart->wk_en);
330 /* Ensure IOPAD wake-enables are cleared */
331 if (cpu_is_omap34xx() && uart->padconf) {
332 u16 v = omap_ctrl_readw(uart->padconf);
333 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
334 omap_ctrl_writew(v, uart->padconf);
338 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
345 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
346 * in Smartidle Mode When Configured for DMA Operations.
348 if (uart->dma_enabled)
349 idlemode = HWMOD_IDLEMODE_FORCE;
351 idlemode = HWMOD_IDLEMODE_SMART;
353 idlemode = HWMOD_IDLEMODE_NO;
356 omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
359 static void omap_uart_block_sleep(struct omap_uart_state *uart)
361 omap_uart_enable_clocks(uart);
363 omap_uart_smart_idle_enable(uart, 0);
366 mod_timer(&uart->timer, jiffies + uart->timeout);
368 del_timer(&uart->timer);
371 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
373 if (device_may_wakeup(&uart->pdev->dev))
374 omap_uart_enable_wakeup(uart);
376 omap_uart_disable_wakeup(uart);
381 omap_uart_smart_idle_enable(uart, 1);
383 del_timer(&uart->timer);
386 static void omap_uart_idle_timer(unsigned long data)
388 struct omap_uart_state *uart = (struct omap_uart_state *)data;
390 omap_uart_allow_sleep(uart);
393 void omap_uart_prepare_idle(int num)
395 struct omap_uart_state *uart;
397 list_for_each_entry(uart, &uart_list, node) {
398 if (num == uart->num && uart->can_sleep) {
399 omap_uart_disable_clocks(uart);
405 void omap_uart_resume_idle(int num)
407 struct omap_uart_state *uart;
409 list_for_each_entry(uart, &uart_list, node) {
410 if (num == uart->num && uart->can_sleep) {
411 omap_uart_enable_clocks(uart);
413 /* Check for IO pad wakeup */
414 if (cpu_is_omap34xx() && uart->padconf) {
415 u16 p = omap_ctrl_readw(uart->padconf);
417 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
418 omap_uart_block_sleep(uart);
421 /* Check for normal UART wakeup */
422 if (__raw_readl(uart->wk_st) & uart->wk_mask)
423 omap_uart_block_sleep(uart);
429 void omap_uart_prepare_suspend(void)
431 struct omap_uart_state *uart;
433 list_for_each_entry(uart, &uart_list, node) {
434 omap_uart_allow_sleep(uart);
438 int omap_uart_can_sleep(void)
440 struct omap_uart_state *uart;
443 list_for_each_entry(uart, &uart_list, node) {
447 if (!uart->can_sleep) {
452 /* This UART can now safely sleep. */
453 omap_uart_allow_sleep(uart);
460 * omap_uart_interrupt()
462 * This handler is used only to detect that *any* UART interrupt has
463 * occurred. It does _nothing_ to handle the interrupt. Rather,
464 * any UART interrupt will trigger the inactivity timer so the
465 * UART will not idle or sleep for its timeout period.
468 /* static int first_interrupt; */
469 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
471 struct omap_uart_state *uart = dev_id;
473 omap_uart_block_sleep(uart);
478 static void omap_uart_idle_init(struct omap_uart_state *uart)
483 uart->timeout = DEFAULT_TIMEOUT;
484 setup_timer(&uart->timer, omap_uart_idle_timer,
485 (unsigned long) uart);
487 mod_timer(&uart->timer, jiffies + uart->timeout);
488 omap_uart_smart_idle_enable(uart, 0);
490 if (cpu_is_omap34xx()) {
491 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
495 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
496 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
499 wk_mask = OMAP3430_ST_UART1_MASK;
503 wk_mask = OMAP3430_ST_UART2_MASK;
507 wk_mask = OMAP3430_ST_UART3_MASK;
511 wk_mask = OMAP3630_ST_UART4_MASK;
515 uart->wk_mask = wk_mask;
516 uart->padconf = padconf;
517 } else if (cpu_is_omap24xx()) {
519 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
523 wk_mask = OMAP24XX_ST_UART1_MASK;
526 wk_mask = OMAP24XX_ST_UART2_MASK;
529 wk_en = OMAP24XX_PM_WKEN2;
530 wk_st = OMAP24XX_PM_WKST2;
531 wk_mask = OMAP24XX_ST_UART3_MASK;
534 uart->wk_mask = wk_mask;
535 if (cpu_is_omap2430()) {
536 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
537 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
538 } else if (cpu_is_omap2420()) {
539 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
540 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
549 uart->irqflags |= IRQF_SHARED;
550 ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
551 IRQF_SHARED, "serial idle", (void *)uart);
555 void omap_uart_enable_irqs(int enable)
558 struct omap_uart_state *uart;
560 list_for_each_entry(uart, &uart_list, node) {
562 pm_runtime_put_sync(&uart->pdev->dev);
563 ret = request_threaded_irq(uart->irq, NULL,
569 pm_runtime_get_noresume(&uart->pdev->dev);
570 free_irq(uart->irq, (void *)uart);
575 static ssize_t sleep_timeout_show(struct device *dev,
576 struct device_attribute *attr,
579 struct platform_device *pdev = to_platform_device(dev);
580 struct omap_device *odev = to_omap_device(pdev);
581 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
583 return sprintf(buf, "%u\n", uart->timeout / HZ);
586 static ssize_t sleep_timeout_store(struct device *dev,
587 struct device_attribute *attr,
588 const char *buf, size_t n)
590 struct platform_device *pdev = to_platform_device(dev);
591 struct omap_device *odev = to_omap_device(pdev);
592 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
595 if (sscanf(buf, "%u", &value) != 1) {
596 dev_err(dev, "sleep_timeout_store: Invalid value\n");
600 uart->timeout = value * HZ;
602 mod_timer(&uart->timer, jiffies + uart->timeout);
604 /* A zero value means disable timeout feature */
605 omap_uart_block_sleep(uart);
610 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
611 sleep_timeout_store);
612 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
614 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
615 static void omap_uart_block_sleep(struct omap_uart_state *uart)
617 /* Needed to enable UART clocks when built without CONFIG_PM */
618 omap_uart_enable_clocks(uart);
620 #define DEV_CREATE_FILE(dev, attr)
621 #endif /* CONFIG_PM */
623 #ifndef CONFIG_SERIAL_OMAP
625 * Override the default 8250 read handler: mem_serial_in()
626 * Empty RX fifo read causes an abort on omap3630 and omap4
627 * This function makes sure that an empty rx fifo is not read on these silicons
628 * (OMAP1/2/3430 are not affected)
630 static unsigned int serial_in_override(struct uart_port *up, int offset)
632 if (UART_RX == offset) {
634 lsr = __serial_read_reg(up, UART_LSR);
635 if (!(lsr & UART_LSR_DR))
639 return __serial_read_reg(up, offset);
642 static void serial_out_override(struct uart_port *up, int offset, int value)
644 unsigned int status, tmout = 10000;
646 status = __serial_read_reg(up, UART_LSR);
647 while (!(status & UART_LSR_THRE)) {
648 /* Wait up to 10ms for the character(s) to be sent. */
652 status = __serial_read_reg(up, UART_LSR);
654 __serial_write_reg(up, offset, value);
658 void __init omap_serial_early_init(void)
663 char oh_name[MAX_UART_HWMOD_NAME_LEN];
664 struct omap_hwmod *oh;
665 struct omap_uart_state *uart;
667 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
669 oh = omap_hwmod_lookup(oh_name);
673 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
679 list_add_tail(&uart->node, &uart_list);
683 * NOTE: omap_hwmod_init() has not yet been called,
684 * so no hwmod functions will work yet.
688 * During UART early init, device need to be probed
689 * to determine SoC specific init before omap_device
690 * is ready. Therefore, don't allow idle here
692 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
697 * omap_serial_init_port() - initialize single serial port
698 * @port: serial port number (0-3)
700 * This function initialies serial driver for given @port only.
701 * Platforms can call this function instead of omap_serial_init()
702 * if they don't plan to use all available UARTs as serial ports.
704 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
705 * use only one of the two.
707 void __init omap_serial_init_port(int port)
709 struct omap_uart_state *uart;
710 struct omap_hwmod *oh;
711 struct omap_device *od;
715 #ifndef CONFIG_SERIAL_OMAP
716 struct plat_serial8250_port ports[2] = {
720 struct plat_serial8250_port *p = &ports[0];
722 struct omap_uart_port_info omap_up;
725 if (WARN_ON(port < 0))
727 if (WARN_ON(port >= num_uarts))
730 list_for_each_entry(uart, &uart_list, node)
731 if (port == uart->num)
735 uart->dma_enabled = 0;
736 #ifndef CONFIG_SERIAL_OMAP
740 * !! 8250 driver does not use standard IORESOURCE* It
741 * has it's own custom pdata that can be taken from
742 * the hwmod resource data. But, this needs to be
743 * done after the build.
745 * ?? does it have to be done before the register ??
746 * YES, because platform_device_data_add() copies
747 * pdata, it does not use a pointer.
749 p->flags = UPF_BOOT_AUTOCONF;
750 p->iotype = UPIO_MEM;
752 p->uartclk = OMAP24XX_BASE_BAUD * 16;
753 p->irq = oh->mpu_irqs[0].irq;
754 p->mapbase = oh->slaves[0]->addr->pa_start;
755 p->membase = omap_hwmod_get_mpu_rt_va(oh);
756 p->irqflags = IRQF_SHARED;
757 p->private_data = uart;
760 * omap44xx: Never read empty UART fifo
761 * omap3xxx: Never read empty UART fifo on UARTs
764 uart->regshift = p->regshift;
765 uart->membase = p->membase;
766 if (cpu_is_omap44xx())
767 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
768 else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
769 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
770 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
772 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
773 p->serial_in = serial_in_override;
774 p->serial_out = serial_out_override;
778 pdata_size = 2 * sizeof(struct plat_serial8250_port);
783 omap_up.dma_enabled = uart->dma_enabled;
784 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
785 omap_up.mapbase = oh->slaves[0]->addr->pa_start;
786 omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
787 omap_up.irqflags = IRQF_SHARED;
788 omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
791 pdata_size = sizeof(struct omap_uart_port_info);
797 od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
799 ARRAY_SIZE(omap_uart_latency), false);
800 WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
803 uart->irq = oh->mpu_irqs[0].irq;
805 uart->mapbase = oh->slaves[0]->addr->pa_start;
806 uart->membase = omap_hwmod_get_mpu_rt_va(oh);
807 uart->pdev = &od->pdev;
811 acquire_console_sem(); /* in case the earlycon is on the UART */
814 * Because of early UART probing, UART did not get idled
815 * on init. Now that omap_device is ready, ensure full idle
816 * before doing omap_device_enable().
818 omap_hwmod_idle(uart->oh);
820 omap_device_enable(uart->pdev);
821 omap_uart_idle_init(uart);
822 omap_uart_reset(uart);
823 omap_hwmod_enable_wakeup(uart->oh);
824 omap_device_idle(uart->pdev);
827 * Need to block sleep long enough for interrupt driven
828 * driver to start. Console driver is in polling mode
829 * so device needs to be kept enabled while polling driver
833 uart->timeout = (30 * HZ);
834 omap_uart_block_sleep(uart);
835 uart->timeout = DEFAULT_TIMEOUT;
837 release_console_sem();
839 if ((cpu_is_omap34xx() && uart->padconf) ||
840 (uart->wk_en && uart->wk_mask)) {
841 device_init_wakeup(&od->pdev.dev, true);
842 DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
845 /* Enable the MDR1 errata for OMAP3 */
846 if (cpu_is_omap34xx())
847 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
851 * omap_serial_init() - initialize all supported serial ports
853 * Initializes all available UARTs as serial ports. Platforms
854 * can call this function when they want to have default behaviour
855 * for serial ports (e.g initialize them all as serial ports).
857 void __init omap_serial_init(void)
859 struct omap_uart_state *uart;
861 list_for_each_entry(uart, &uart_list, node)
862 omap_serial_init_port(uart->num);