2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
27 #include <plat/common.h>
28 #include <plat/board.h>
29 #include <plat/clock.h>
30 #include <plat/control.h>
34 #include "prm-regbits-34xx.h"
36 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
38 #define DEFAULT_TIMEOUT (5 * HZ)
40 struct omap_uart_state {
43 struct timer_list timer;
55 struct plat_serial8250_port *p;
56 struct list_head node;
57 struct platform_device pdev;
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
62 /* Registers to be saved/restored for OFF-mode */
72 static LIST_HEAD(uart_list);
74 static struct plat_serial8250_port serial_platform_data0[] = {
76 .mapbase = OMAP_UART1_BASE,
78 .flags = UPF_BOOT_AUTOCONF,
81 .uartclk = OMAP24XX_BASE_BAUD * 16,
87 static struct plat_serial8250_port serial_platform_data1[] = {
89 .mapbase = OMAP_UART2_BASE,
91 .flags = UPF_BOOT_AUTOCONF,
94 .uartclk = OMAP24XX_BASE_BAUD * 16,
100 static struct plat_serial8250_port serial_platform_data2[] = {
102 .mapbase = OMAP_UART3_BASE,
104 .flags = UPF_BOOT_AUTOCONF,
107 .uartclk = OMAP24XX_BASE_BAUD * 16,
113 #ifdef CONFIG_ARCH_OMAP4
114 static struct plat_serial8250_port serial_platform_data3[] = {
116 .mapbase = OMAP_UART4_BASE,
118 .flags = UPF_BOOT_AUTOCONF,
121 .uartclk = OMAP24XX_BASE_BAUD * 16,
127 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
130 offset <<= up->regshift;
131 return (unsigned int)__raw_readb(up->membase + offset);
134 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
137 offset <<= p->regshift;
138 __raw_writeb(value, p->membase + offset);
142 * Internal UARTs need to be initialized for the 8250 autoconfig to work
143 * properly. Note that the TX watermark initialization may not be needed
144 * once the 8250.c watermark handling code is merged.
146 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
148 struct plat_serial8250_port *p = uart->p;
150 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
151 serial_write_reg(p, UART_OMAP_SCR, 0x08);
152 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
153 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
156 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
158 static void omap_uart_save_context(struct omap_uart_state *uart)
161 struct plat_serial8250_port *p = uart->p;
163 if (!enable_off_mode)
166 lcr = serial_read_reg(p, UART_LCR);
167 serial_write_reg(p, UART_LCR, 0xBF);
168 uart->dll = serial_read_reg(p, UART_DLL);
169 uart->dlh = serial_read_reg(p, UART_DLM);
170 serial_write_reg(p, UART_LCR, lcr);
171 uart->ier = serial_read_reg(p, UART_IER);
172 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
173 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
174 uart->wer = serial_read_reg(p, UART_OMAP_WER);
176 uart->context_valid = 1;
179 static void omap_uart_restore_context(struct omap_uart_state *uart)
182 struct plat_serial8250_port *p = uart->p;
184 if (!enable_off_mode)
187 if (!uart->context_valid)
190 uart->context_valid = 0;
192 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
193 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
194 efr = serial_read_reg(p, UART_EFR);
195 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
196 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
197 serial_write_reg(p, UART_IER, 0x0);
198 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
199 serial_write_reg(p, UART_DLL, uart->dll);
200 serial_write_reg(p, UART_DLM, uart->dlh);
201 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
202 serial_write_reg(p, UART_IER, uart->ier);
203 serial_write_reg(p, UART_FCR, 0xA1);
204 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
205 serial_write_reg(p, UART_EFR, efr);
206 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
207 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
208 serial_write_reg(p, UART_OMAP_WER, uart->wer);
209 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
210 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
213 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
214 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
215 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
217 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
222 clk_enable(uart->ick);
223 clk_enable(uart->fck);
225 omap_uart_restore_context(uart);
230 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
235 omap_uart_save_context(uart);
237 clk_disable(uart->ick);
238 clk_disable(uart->fck);
241 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
243 /* Set wake-enable bit */
244 if (uart->wk_en && uart->wk_mask) {
245 u32 v = __raw_readl(uart->wk_en);
247 __raw_writel(v, uart->wk_en);
250 /* Ensure IOPAD wake-enables are set */
251 if (cpu_is_omap34xx() && uart->padconf) {
252 u16 v = omap_ctrl_readw(uart->padconf);
253 v |= OMAP3_PADCONF_WAKEUPENABLE0;
254 omap_ctrl_writew(v, uart->padconf);
258 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
260 /* Clear wake-enable bit */
261 if (uart->wk_en && uart->wk_mask) {
262 u32 v = __raw_readl(uart->wk_en);
264 __raw_writel(v, uart->wk_en);
267 /* Ensure IOPAD wake-enables are cleared */
268 if (cpu_is_omap34xx() && uart->padconf) {
269 u16 v = omap_ctrl_readw(uart->padconf);
270 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
271 omap_ctrl_writew(v, uart->padconf);
275 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
278 struct plat_serial8250_port *p = uart->p;
281 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
287 serial_write_reg(p, UART_OMAP_SYSC, sysc);
290 static void omap_uart_block_sleep(struct omap_uart_state *uart)
292 omap_uart_enable_clocks(uart);
294 omap_uart_smart_idle_enable(uart, 0);
297 mod_timer(&uart->timer, jiffies + uart->timeout);
299 del_timer(&uart->timer);
302 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
304 if (device_may_wakeup(&uart->pdev.dev))
305 omap_uart_enable_wakeup(uart);
307 omap_uart_disable_wakeup(uart);
312 omap_uart_smart_idle_enable(uart, 1);
314 del_timer(&uart->timer);
317 static void omap_uart_idle_timer(unsigned long data)
319 struct omap_uart_state *uart = (struct omap_uart_state *)data;
321 omap_uart_allow_sleep(uart);
324 void omap_uart_prepare_idle(int num)
326 struct omap_uart_state *uart;
328 list_for_each_entry(uart, &uart_list, node) {
329 if (num == uart->num && uart->can_sleep) {
330 omap_uart_disable_clocks(uart);
336 void omap_uart_resume_idle(int num)
338 struct omap_uart_state *uart;
340 list_for_each_entry(uart, &uart_list, node) {
341 if (num == uart->num) {
342 omap_uart_enable_clocks(uart);
344 /* Check for IO pad wakeup */
345 if (cpu_is_omap34xx() && uart->padconf) {
346 u16 p = omap_ctrl_readw(uart->padconf);
348 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
349 omap_uart_block_sleep(uart);
352 /* Check for normal UART wakeup */
353 if (__raw_readl(uart->wk_st) & uart->wk_mask)
354 omap_uart_block_sleep(uart);
360 void omap_uart_prepare_suspend(void)
362 struct omap_uart_state *uart;
364 list_for_each_entry(uart, &uart_list, node) {
365 omap_uart_allow_sleep(uart);
369 int omap_uart_can_sleep(void)
371 struct omap_uart_state *uart;
374 list_for_each_entry(uart, &uart_list, node) {
378 if (!uart->can_sleep) {
383 /* This UART can now safely sleep. */
384 omap_uart_allow_sleep(uart);
391 * omap_uart_interrupt()
393 * This handler is used only to detect that *any* UART interrupt has
394 * occurred. It does _nothing_ to handle the interrupt. Rather,
395 * any UART interrupt will trigger the inactivity timer so the
396 * UART will not idle or sleep for its timeout period.
399 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
401 struct omap_uart_state *uart = dev_id;
403 omap_uart_block_sleep(uart);
408 static void omap_uart_idle_init(struct omap_uart_state *uart)
410 struct plat_serial8250_port *p = uart->p;
414 uart->timeout = DEFAULT_TIMEOUT;
415 setup_timer(&uart->timer, omap_uart_idle_timer,
416 (unsigned long) uart);
417 mod_timer(&uart->timer, jiffies + uart->timeout);
418 omap_uart_smart_idle_enable(uart, 0);
420 if (cpu_is_omap34xx()) {
421 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
425 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
426 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
429 wk_mask = OMAP3430_ST_UART1_MASK;
433 wk_mask = OMAP3430_ST_UART2_MASK;
437 wk_mask = OMAP3430_ST_UART3_MASK;
441 uart->wk_mask = wk_mask;
442 uart->padconf = padconf;
443 } else if (cpu_is_omap24xx()) {
446 if (cpu_is_omap2430()) {
447 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
448 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
449 } else if (cpu_is_omap2420()) {
450 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
451 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
455 wk_mask = OMAP24XX_ST_UART1_MASK;
458 wk_mask = OMAP24XX_ST_UART2_MASK;
461 wk_mask = OMAP24XX_ST_UART3_MASK;
464 uart->wk_mask = wk_mask;
472 p->irqflags |= IRQF_SHARED;
473 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
474 "serial idle", (void *)uart);
478 void omap_uart_enable_irqs(int enable)
481 struct omap_uart_state *uart;
483 list_for_each_entry(uart, &uart_list, node) {
485 ret = request_irq(uart->p->irq, omap_uart_interrupt,
486 IRQF_SHARED, "serial idle", (void *)uart);
488 free_irq(uart->p->irq, (void *)uart);
492 static ssize_t sleep_timeout_show(struct device *dev,
493 struct device_attribute *attr,
496 struct platform_device *pdev = container_of(dev,
497 struct platform_device, dev);
498 struct omap_uart_state *uart = container_of(pdev,
499 struct omap_uart_state, pdev);
501 return sprintf(buf, "%u\n", uart->timeout / HZ);
504 static ssize_t sleep_timeout_store(struct device *dev,
505 struct device_attribute *attr,
506 const char *buf, size_t n)
508 struct platform_device *pdev = container_of(dev,
509 struct platform_device, dev);
510 struct omap_uart_state *uart = container_of(pdev,
511 struct omap_uart_state, pdev);
514 if (sscanf(buf, "%u", &value) != 1) {
515 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
519 uart->timeout = value * HZ;
521 mod_timer(&uart->timer, jiffies + uart->timeout);
523 /* A zero value means disable timeout feature */
524 omap_uart_block_sleep(uart);
529 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
530 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
532 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
533 #define DEV_CREATE_FILE(dev, attr)
534 #endif /* CONFIG_PM */
536 static struct omap_uart_state omap_uart[] = {
539 .name = "serial8250",
540 .id = PLAT8250_DEV_PLATFORM,
542 .platform_data = serial_platform_data0,
547 .name = "serial8250",
548 .id = PLAT8250_DEV_PLATFORM1,
550 .platform_data = serial_platform_data1,
555 .name = "serial8250",
556 .id = PLAT8250_DEV_PLATFORM2,
558 .platform_data = serial_platform_data2,
562 #ifdef CONFIG_ARCH_OMAP4
565 .name = "serial8250",
568 .platform_data = serial_platform_data3,
575 void __init omap_serial_early_init(void)
581 * Make sure the serial ports are muxed on at this point.
582 * You have to mux them off in device drivers later on
586 for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
587 struct omap_uart_state *uart = &omap_uart[i];
588 struct platform_device *pdev = &uart->pdev;
589 struct device *dev = &pdev->dev;
590 struct plat_serial8250_port *p = dev->platform_data;
593 * Module 4KB + L4 interconnect 4KB
594 * Static mapping, never released
596 p->membase = ioremap(p->mapbase, SZ_8K);
598 printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
602 sprintf(name, "uart%d_ick", i+1);
603 uart->ick = clk_get(NULL, name);
604 if (IS_ERR(uart->ick)) {
605 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
609 sprintf(name, "uart%d_fck", i+1);
610 uart->fck = clk_get(NULL, name);
611 if (IS_ERR(uart->fck)) {
612 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
616 /* FIXME: Remove this once the clkdev is ready */
617 if (!cpu_is_omap44xx()) {
618 if (!uart->ick || !uart->fck)
623 p->private_data = uart;
625 list_add_tail(&uart->node, &uart_list);
627 if (cpu_is_omap44xx())
630 omap_uart_enable_clocks(uart);
634 void __init omap_serial_init(void)
638 for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
639 struct omap_uart_state *uart = &omap_uart[i];
640 struct platform_device *pdev = &uart->pdev;
641 struct device *dev = &pdev->dev;
643 omap_uart_reset(uart);
644 omap_uart_idle_init(uart);
646 if (WARN_ON(platform_device_register(pdev)))
648 if ((cpu_is_omap34xx() && uart->padconf) ||
649 (uart->wk_en && uart->wk_mask)) {
650 device_init_wakeup(dev, true);
651 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);