2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
27 #include <plat/common.h>
28 #include <plat/board.h>
29 #include <plat/clock.h>
30 #include <plat/control.h>
34 #include "prm-regbits-34xx.h"
36 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
37 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
39 #define DEFAULT_TIMEOUT (5 * HZ)
41 struct omap_uart_state {
44 struct timer_list timer;
56 struct plat_serial8250_port *p;
57 struct list_head node;
58 struct platform_device pdev;
60 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
63 /* Registers to be saved/restored for OFF-mode */
73 static LIST_HEAD(uart_list);
75 static struct plat_serial8250_port serial_platform_data0[] = {
77 .mapbase = OMAP_UART1_BASE,
79 .flags = UPF_BOOT_AUTOCONF,
82 .uartclk = OMAP24XX_BASE_BAUD * 16,
88 static struct plat_serial8250_port serial_platform_data1[] = {
90 .mapbase = OMAP_UART2_BASE,
92 .flags = UPF_BOOT_AUTOCONF,
95 .uartclk = OMAP24XX_BASE_BAUD * 16,
101 static struct plat_serial8250_port serial_platform_data2[] = {
103 .mapbase = OMAP_UART3_BASE,
105 .flags = UPF_BOOT_AUTOCONF,
108 .uartclk = OMAP24XX_BASE_BAUD * 16,
114 #ifdef CONFIG_ARCH_OMAP4
115 static struct plat_serial8250_port serial_platform_data3[] = {
117 .mapbase = OMAP_UART4_BASE,
119 .flags = UPF_BOOT_AUTOCONF,
122 .uartclk = OMAP24XX_BASE_BAUD * 16,
128 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
131 offset <<= up->regshift;
132 return (unsigned int)__raw_readb(up->membase + offset);
135 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
138 offset <<= p->regshift;
139 __raw_writeb(value, p->membase + offset);
143 * Internal UARTs need to be initialized for the 8250 autoconfig to work
144 * properly. Note that the TX watermark initialization may not be needed
145 * once the 8250.c watermark handling code is merged.
147 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
149 struct plat_serial8250_port *p = uart->p;
151 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
152 serial_write_reg(p, UART_OMAP_SCR, 0x08);
153 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
154 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
157 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
159 static void omap_uart_save_context(struct omap_uart_state *uart)
162 struct plat_serial8250_port *p = uart->p;
164 if (!enable_off_mode)
167 lcr = serial_read_reg(p, UART_LCR);
168 serial_write_reg(p, UART_LCR, 0xBF);
169 uart->dll = serial_read_reg(p, UART_DLL);
170 uart->dlh = serial_read_reg(p, UART_DLM);
171 serial_write_reg(p, UART_LCR, lcr);
172 uart->ier = serial_read_reg(p, UART_IER);
173 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
174 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
175 uart->wer = serial_read_reg(p, UART_OMAP_WER);
177 uart->context_valid = 1;
180 static void omap_uart_restore_context(struct omap_uart_state *uart)
183 struct plat_serial8250_port *p = uart->p;
185 if (!enable_off_mode)
188 if (!uart->context_valid)
191 uart->context_valid = 0;
193 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
194 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
195 efr = serial_read_reg(p, UART_EFR);
196 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
197 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
198 serial_write_reg(p, UART_IER, 0x0);
199 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
200 serial_write_reg(p, UART_DLL, uart->dll);
201 serial_write_reg(p, UART_DLM, uart->dlh);
202 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
203 serial_write_reg(p, UART_IER, uart->ier);
204 serial_write_reg(p, UART_FCR, 0xA1);
205 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
206 serial_write_reg(p, UART_EFR, efr);
207 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
208 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
209 serial_write_reg(p, UART_OMAP_WER, uart->wer);
210 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
211 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
214 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
215 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
216 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
218 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
223 clk_enable(uart->ick);
224 clk_enable(uart->fck);
226 omap_uart_restore_context(uart);
231 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
236 omap_uart_save_context(uart);
238 clk_disable(uart->ick);
239 clk_disable(uart->fck);
242 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
244 /* Set wake-enable bit */
245 if (uart->wk_en && uart->wk_mask) {
246 u32 v = __raw_readl(uart->wk_en);
248 __raw_writel(v, uart->wk_en);
251 /* Ensure IOPAD wake-enables are set */
252 if (cpu_is_omap34xx() && uart->padconf) {
253 u16 v = omap_ctrl_readw(uart->padconf);
254 v |= OMAP3_PADCONF_WAKEUPENABLE0;
255 omap_ctrl_writew(v, uart->padconf);
259 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
261 /* Clear wake-enable bit */
262 if (uart->wk_en && uart->wk_mask) {
263 u32 v = __raw_readl(uart->wk_en);
265 __raw_writel(v, uart->wk_en);
268 /* Ensure IOPAD wake-enables are cleared */
269 if (cpu_is_omap34xx() && uart->padconf) {
270 u16 v = omap_ctrl_readw(uart->padconf);
271 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
272 omap_ctrl_writew(v, uart->padconf);
276 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
279 struct plat_serial8250_port *p = uart->p;
282 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
288 serial_write_reg(p, UART_OMAP_SYSC, sysc);
291 static void omap_uart_block_sleep(struct omap_uart_state *uart)
293 omap_uart_enable_clocks(uart);
295 omap_uart_smart_idle_enable(uart, 0);
298 mod_timer(&uart->timer, jiffies + uart->timeout);
300 del_timer(&uart->timer);
303 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
305 if (device_may_wakeup(&uart->pdev.dev))
306 omap_uart_enable_wakeup(uart);
308 omap_uart_disable_wakeup(uart);
313 omap_uart_smart_idle_enable(uart, 1);
315 del_timer(&uart->timer);
318 static void omap_uart_idle_timer(unsigned long data)
320 struct omap_uart_state *uart = (struct omap_uart_state *)data;
322 omap_uart_allow_sleep(uart);
325 void omap_uart_prepare_idle(int num)
327 struct omap_uart_state *uart;
329 list_for_each_entry(uart, &uart_list, node) {
330 if (num == uart->num && uart->can_sleep) {
331 omap_uart_disable_clocks(uart);
337 void omap_uart_resume_idle(int num)
339 struct omap_uart_state *uart;
341 list_for_each_entry(uart, &uart_list, node) {
342 if (num == uart->num) {
343 omap_uart_enable_clocks(uart);
345 /* Check for IO pad wakeup */
346 if (cpu_is_omap34xx() && uart->padconf) {
347 u16 p = omap_ctrl_readw(uart->padconf);
349 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
350 omap_uart_block_sleep(uart);
353 /* Check for normal UART wakeup */
354 if (__raw_readl(uart->wk_st) & uart->wk_mask)
355 omap_uart_block_sleep(uart);
361 void omap_uart_prepare_suspend(void)
363 struct omap_uart_state *uart;
365 list_for_each_entry(uart, &uart_list, node) {
366 omap_uart_allow_sleep(uart);
370 int omap_uart_can_sleep(void)
372 struct omap_uart_state *uart;
375 list_for_each_entry(uart, &uart_list, node) {
379 if (!uart->can_sleep) {
384 /* This UART can now safely sleep. */
385 omap_uart_allow_sleep(uart);
392 * omap_uart_interrupt()
394 * This handler is used only to detect that *any* UART interrupt has
395 * occurred. It does _nothing_ to handle the interrupt. Rather,
396 * any UART interrupt will trigger the inactivity timer so the
397 * UART will not idle or sleep for its timeout period.
400 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
402 struct omap_uart_state *uart = dev_id;
404 omap_uart_block_sleep(uart);
409 static void omap_uart_idle_init(struct omap_uart_state *uart)
411 struct plat_serial8250_port *p = uart->p;
415 uart->timeout = DEFAULT_TIMEOUT;
416 setup_timer(&uart->timer, omap_uart_idle_timer,
417 (unsigned long) uart);
418 mod_timer(&uart->timer, jiffies + uart->timeout);
419 omap_uart_smart_idle_enable(uart, 0);
421 if (cpu_is_omap34xx()) {
422 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
426 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
427 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
430 wk_mask = OMAP3430_ST_UART1_MASK;
434 wk_mask = OMAP3430_ST_UART2_MASK;
438 wk_mask = OMAP3430_ST_UART3_MASK;
442 uart->wk_mask = wk_mask;
443 uart->padconf = padconf;
444 } else if (cpu_is_omap24xx()) {
447 if (cpu_is_omap2430()) {
448 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
449 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
450 } else if (cpu_is_omap2420()) {
451 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
452 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
456 wk_mask = OMAP24XX_ST_UART1_MASK;
459 wk_mask = OMAP24XX_ST_UART2_MASK;
462 wk_mask = OMAP24XX_ST_UART3_MASK;
465 uart->wk_mask = wk_mask;
473 p->irqflags |= IRQF_SHARED;
474 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
475 "serial idle", (void *)uart);
479 void omap_uart_enable_irqs(int enable)
482 struct omap_uart_state *uart;
484 list_for_each_entry(uart, &uart_list, node) {
486 ret = request_irq(uart->p->irq, omap_uart_interrupt,
487 IRQF_SHARED, "serial idle", (void *)uart);
489 free_irq(uart->p->irq, (void *)uart);
493 static ssize_t sleep_timeout_show(struct device *dev,
494 struct device_attribute *attr,
497 struct platform_device *pdev = container_of(dev,
498 struct platform_device, dev);
499 struct omap_uart_state *uart = container_of(pdev,
500 struct omap_uart_state, pdev);
502 return sprintf(buf, "%u\n", uart->timeout / HZ);
505 static ssize_t sleep_timeout_store(struct device *dev,
506 struct device_attribute *attr,
507 const char *buf, size_t n)
509 struct platform_device *pdev = container_of(dev,
510 struct platform_device, dev);
511 struct omap_uart_state *uart = container_of(pdev,
512 struct omap_uart_state, pdev);
515 if (sscanf(buf, "%u", &value) != 1) {
516 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
520 uart->timeout = value * HZ;
522 mod_timer(&uart->timer, jiffies + uart->timeout);
524 /* A zero value means disable timeout feature */
525 omap_uart_block_sleep(uart);
530 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
531 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
533 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
534 #define DEV_CREATE_FILE(dev, attr)
535 #endif /* CONFIG_PM */
537 static struct omap_uart_state omap_uart[] = {
540 .name = "serial8250",
541 .id = PLAT8250_DEV_PLATFORM,
543 .platform_data = serial_platform_data0,
548 .name = "serial8250",
549 .id = PLAT8250_DEV_PLATFORM1,
551 .platform_data = serial_platform_data1,
556 .name = "serial8250",
557 .id = PLAT8250_DEV_PLATFORM2,
559 .platform_data = serial_platform_data2,
563 #ifdef CONFIG_ARCH_OMAP4
566 .name = "serial8250",
569 .platform_data = serial_platform_data3,
577 * Override the default 8250 read handler: mem_serial_in()
578 * Empty RX fifo read causes an abort on omap3630 and omap4
579 * This function makes sure that an empty rx fifo is not read on these silicons
580 * (OMAP1/2/3430 are not affected)
582 static unsigned int serial_in_override(struct uart_port *up, int offset)
584 if (UART_RX == offset) {
586 lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR);
587 if (!(lsr & UART_LSR_DR))
590 return serial_read_reg(omap_uart[up->line].p, offset);
593 void __init omap_serial_early_init(void)
599 * Make sure the serial ports are muxed on at this point.
600 * You have to mux them off in device drivers later on
604 for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
605 struct omap_uart_state *uart = &omap_uart[i];
606 struct platform_device *pdev = &uart->pdev;
607 struct device *dev = &pdev->dev;
608 struct plat_serial8250_port *p = dev->platform_data;
611 * Module 4KB + L4 interconnect 4KB
612 * Static mapping, never released
614 p->membase = ioremap(p->mapbase, SZ_8K);
616 printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
620 sprintf(name, "uart%d_ick", i+1);
621 uart->ick = clk_get(NULL, name);
622 if (IS_ERR(uart->ick)) {
623 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
627 sprintf(name, "uart%d_fck", i+1);
628 uart->fck = clk_get(NULL, name);
629 if (IS_ERR(uart->fck)) {
630 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
634 /* FIXME: Remove this once the clkdev is ready */
635 if (!cpu_is_omap44xx()) {
636 if (!uart->ick || !uart->fck)
641 p->private_data = uart;
643 list_add_tail(&uart->node, &uart_list);
645 if (cpu_is_omap44xx())
648 omap_uart_enable_clocks(uart);
653 * omap_serial_init_port() - initialize single serial port
654 * @port: serial port number (0-3)
656 * This function initialies serial driver for given @port only.
657 * Platforms can call this function instead of omap_serial_init()
658 * if they don't plan to use all available UARTs as serial ports.
660 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
661 * use only one of the two.
663 void __init omap_serial_init_port(int port)
665 struct omap_uart_state *uart;
666 struct platform_device *pdev;
670 BUG_ON(port >= ARRAY_SIZE(omap_uart));
672 uart = &omap_uart[port];
676 omap_uart_reset(uart);
677 omap_uart_idle_init(uart);
679 if (WARN_ON(platform_device_register(pdev)))
682 if ((cpu_is_omap34xx() && uart->padconf) ||
683 (uart->wk_en && uart->wk_mask)) {
684 device_init_wakeup(dev, true);
685 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
688 /* omap44xx: Never read empty UART fifo
689 * omap3xxx: Never read empty UART fifo on UARTs
692 if (cpu_is_omap44xx())
693 uart->p->serial_in = serial_in_override;
694 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
695 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
696 uart->p->serial_in = serial_in_override;
700 * omap_serial_init() - intialize all supported serial ports
702 * Initializes all available UARTs as serial ports. Platforms
703 * can call this function when they want to have default behaviour
704 * for serial ports (e.g initialize them all as serial ports).
706 void __init omap_serial_init(void)
710 for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
711 omap_serial_init_port(i);