2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_reg.h>
23 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/serial_8250.h>
29 #include <linux/pm_runtime.h>
31 #ifdef CONFIG_SERIAL_OMAP
32 #include <plat/omap-serial.h>
35 #include <plat/common.h>
36 #include <plat/board.h>
37 #include <plat/clock.h>
39 #include <plat/omap_hwmod.h>
40 #include <plat/omap_device.h>
45 #include "prm-regbits-34xx.h"
48 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
49 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
51 #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
52 #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
55 * NOTE: By default the serial timeout is disabled as it causes lost characters
56 * over the serial ports. This means that the UART clocks will stay on until
57 * disabled via sysfs. This also causes that any deeper omap sleep states are
60 #define DEFAULT_TIMEOUT 0
62 #define MAX_UART_HWMOD_NAME_LEN 16
64 struct omap_uart_state {
67 struct timer_list timer;
83 void __iomem *membase;
84 resource_size_t mapbase;
86 struct list_head node;
87 struct omap_hwmod *oh;
88 struct platform_device *pdev;
91 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
94 /* Registers to be saved/restored for OFF-mode */
105 static LIST_HEAD(uart_list);
109 * Since these idle/enable hooks are used in the idle path itself
110 * which has interrupts disabled, use the non-locking versions of
111 * the hwmod enable/disable functions.
113 static int uart_idle_hwmod(struct omap_device *od)
115 _omap_hwmod_idle(od->hwmods[0]);
120 static int uart_enable_hwmod(struct omap_device *od)
122 _omap_hwmod_enable(od->hwmods[0]);
127 static struct omap_device_pm_latency omap_uart_latency[] = {
129 .deactivate_func = uart_idle_hwmod,
130 .activate_func = uart_enable_hwmod,
131 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
135 static inline unsigned int __serial_read_reg(struct uart_port *up,
138 offset <<= up->regshift;
139 return (unsigned int)__raw_readb(up->membase + offset);
142 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
145 offset <<= uart->regshift;
146 return (unsigned int)__raw_readb(uart->membase + offset);
149 static inline void __serial_write_reg(struct uart_port *up, int offset,
152 offset <<= up->regshift;
153 __raw_writeb(value, up->membase + offset);
156 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
159 offset <<= uart->regshift;
160 __raw_writeb(value, uart->membase + offset);
164 * Internal UARTs need to be initialized for the 8250 autoconfig to work
165 * properly. Note that the TX watermark initialization may not be needed
166 * once the 8250.c watermark handling code is merged.
169 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
171 serial_write_reg(uart, UART_OMAP_MDR1, 0x07);
172 serial_write_reg(uart, UART_OMAP_SCR, 0x08);
173 serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
176 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
179 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
180 * The access to uart register after MDR1 Access
181 * causes UART to corrupt data.
184 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
185 * give 10 times as much
187 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
192 serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
194 serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
195 UART_FCR_CLEAR_RCVR);
197 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
198 * TX_FIFO_E bit is 1.
200 while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
201 (UART_LSR_THRE | UART_LSR_DR))) {
204 /* Should *never* happen. we warn and carry on */
205 dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
206 serial_read_reg(uart, UART_LSR));
213 static void omap_uart_save_context(struct omap_uart_state *uart)
217 if (!enable_off_mode)
220 lcr = serial_read_reg(uart, UART_LCR);
221 serial_write_reg(uart, UART_LCR, 0xBF);
222 uart->dll = serial_read_reg(uart, UART_DLL);
223 uart->dlh = serial_read_reg(uart, UART_DLM);
224 serial_write_reg(uart, UART_LCR, lcr);
225 uart->ier = serial_read_reg(uart, UART_IER);
226 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
227 uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
228 uart->wer = serial_read_reg(uart, UART_OMAP_WER);
229 serial_write_reg(uart, UART_LCR, 0x80);
230 uart->mcr = serial_read_reg(uart, UART_MCR);
231 serial_write_reg(uart, UART_LCR, lcr);
233 uart->context_valid = 1;
236 static void omap_uart_restore_context(struct omap_uart_state *uart)
240 if (!enable_off_mode)
243 if (!uart->context_valid)
246 uart->context_valid = 0;
248 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
249 omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
251 serial_write_reg(uart, UART_OMAP_MDR1, 0x7);
252 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
253 efr = serial_read_reg(uart, UART_EFR);
254 serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
255 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
256 serial_write_reg(uart, UART_IER, 0x0);
257 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
258 serial_write_reg(uart, UART_DLL, uart->dll);
259 serial_write_reg(uart, UART_DLM, uart->dlh);
260 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
261 serial_write_reg(uart, UART_IER, uart->ier);
262 serial_write_reg(uart, UART_LCR, 0x80);
263 serial_write_reg(uart, UART_MCR, uart->mcr);
264 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
265 serial_write_reg(uart, UART_EFR, efr);
266 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
267 serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
268 serial_write_reg(uart, UART_OMAP_WER, uart->wer);
269 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
270 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
271 omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
274 serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
277 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
278 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
279 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
281 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
286 omap_device_enable(uart->pdev);
288 omap_uart_restore_context(uart);
293 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
298 omap_uart_save_context(uart);
300 omap_device_idle(uart->pdev);
303 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
305 /* Set wake-enable bit */
306 if (uart->wk_en && uart->wk_mask) {
307 u32 v = __raw_readl(uart->wk_en);
309 __raw_writel(v, uart->wk_en);
312 /* Ensure IOPAD wake-enables are set */
313 if (cpu_is_omap34xx() && uart->padconf) {
314 u16 v = omap_ctrl_readw(uart->padconf);
315 v |= OMAP3_PADCONF_WAKEUPENABLE0;
316 omap_ctrl_writew(v, uart->padconf);
320 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
322 /* Clear wake-enable bit */
323 if (uart->wk_en && uart->wk_mask) {
324 u32 v = __raw_readl(uart->wk_en);
326 __raw_writel(v, uart->wk_en);
329 /* Ensure IOPAD wake-enables are cleared */
330 if (cpu_is_omap34xx() && uart->padconf) {
331 u16 v = omap_ctrl_readw(uart->padconf);
332 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
333 omap_ctrl_writew(v, uart->padconf);
337 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
344 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
345 * in Smartidle Mode When Configured for DMA Operations.
347 if (uart->dma_enabled)
348 idlemode = HWMOD_IDLEMODE_FORCE;
350 idlemode = HWMOD_IDLEMODE_SMART;
352 idlemode = HWMOD_IDLEMODE_NO;
355 omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
358 static void omap_uart_block_sleep(struct omap_uart_state *uart)
360 omap_uart_enable_clocks(uart);
362 omap_uart_smart_idle_enable(uart, 0);
365 mod_timer(&uart->timer, jiffies + uart->timeout);
367 del_timer(&uart->timer);
370 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
372 if (device_may_wakeup(&uart->pdev->dev))
373 omap_uart_enable_wakeup(uart);
375 omap_uart_disable_wakeup(uart);
380 omap_uart_smart_idle_enable(uart, 1);
382 del_timer(&uart->timer);
385 static void omap_uart_idle_timer(unsigned long data)
387 struct omap_uart_state *uart = (struct omap_uart_state *)data;
389 omap_uart_allow_sleep(uart);
392 void omap_uart_prepare_idle(int num)
394 struct omap_uart_state *uart;
396 list_for_each_entry(uart, &uart_list, node) {
397 if (num == uart->num && uart->can_sleep) {
398 omap_uart_disable_clocks(uart);
404 void omap_uart_resume_idle(int num)
406 struct omap_uart_state *uart;
408 list_for_each_entry(uart, &uart_list, node) {
409 if (num == uart->num) {
410 omap_uart_enable_clocks(uart);
412 /* Check for IO pad wakeup */
413 if (cpu_is_omap34xx() && uart->padconf) {
414 u16 p = omap_ctrl_readw(uart->padconf);
416 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
417 omap_uart_block_sleep(uart);
420 /* Check for normal UART wakeup */
421 if (__raw_readl(uart->wk_st) & uart->wk_mask)
422 omap_uart_block_sleep(uart);
428 void omap_uart_prepare_suspend(void)
430 struct omap_uart_state *uart;
432 list_for_each_entry(uart, &uart_list, node) {
433 omap_uart_allow_sleep(uart);
437 int omap_uart_can_sleep(void)
439 struct omap_uart_state *uart;
442 list_for_each_entry(uart, &uart_list, node) {
446 if (!uart->can_sleep) {
451 /* This UART can now safely sleep. */
452 omap_uart_allow_sleep(uart);
459 * omap_uart_interrupt()
461 * This handler is used only to detect that *any* UART interrupt has
462 * occurred. It does _nothing_ to handle the interrupt. Rather,
463 * any UART interrupt will trigger the inactivity timer so the
464 * UART will not idle or sleep for its timeout period.
467 /* static int first_interrupt; */
468 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
470 struct omap_uart_state *uart = dev_id;
472 omap_uart_block_sleep(uart);
477 static void omap_uart_idle_init(struct omap_uart_state *uart)
482 uart->timeout = DEFAULT_TIMEOUT;
483 setup_timer(&uart->timer, omap_uart_idle_timer,
484 (unsigned long) uart);
486 mod_timer(&uart->timer, jiffies + uart->timeout);
487 omap_uart_smart_idle_enable(uart, 0);
489 if (cpu_is_omap34xx()) {
490 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
494 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
495 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
498 wk_mask = OMAP3430_ST_UART1_MASK;
502 wk_mask = OMAP3430_ST_UART2_MASK;
506 wk_mask = OMAP3430_ST_UART3_MASK;
510 wk_mask = OMAP3630_ST_UART4_MASK;
514 uart->wk_mask = wk_mask;
515 uart->padconf = padconf;
516 } else if (cpu_is_omap24xx()) {
518 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
522 wk_mask = OMAP24XX_ST_UART1_MASK;
525 wk_mask = OMAP24XX_ST_UART2_MASK;
528 wk_en = OMAP24XX_PM_WKEN2;
529 wk_st = OMAP24XX_PM_WKST2;
530 wk_mask = OMAP24XX_ST_UART3_MASK;
533 uart->wk_mask = wk_mask;
534 if (cpu_is_omap2430()) {
535 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
536 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
537 } else if (cpu_is_omap2420()) {
538 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
539 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
548 uart->irqflags |= IRQF_SHARED;
549 ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
550 IRQF_SHARED, "serial idle", (void *)uart);
554 void omap_uart_enable_irqs(int enable)
557 struct omap_uart_state *uart;
559 list_for_each_entry(uart, &uart_list, node) {
561 pm_runtime_put_sync(&uart->pdev->dev);
562 ret = request_threaded_irq(uart->irq, NULL,
568 pm_runtime_get_noresume(&uart->pdev->dev);
569 free_irq(uart->irq, (void *)uart);
574 static ssize_t sleep_timeout_show(struct device *dev,
575 struct device_attribute *attr,
578 struct platform_device *pdev = to_platform_device(dev);
579 struct omap_device *odev = to_omap_device(pdev);
580 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
582 return sprintf(buf, "%u\n", uart->timeout / HZ);
585 static ssize_t sleep_timeout_store(struct device *dev,
586 struct device_attribute *attr,
587 const char *buf, size_t n)
589 struct platform_device *pdev = to_platform_device(dev);
590 struct omap_device *odev = to_omap_device(pdev);
591 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
594 if (sscanf(buf, "%u", &value) != 1) {
595 dev_err(dev, "sleep_timeout_store: Invalid value\n");
599 uart->timeout = value * HZ;
601 mod_timer(&uart->timer, jiffies + uart->timeout);
603 /* A zero value means disable timeout feature */
604 omap_uart_block_sleep(uart);
609 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
610 sleep_timeout_store);
611 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
613 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
614 static void omap_uart_block_sleep(struct omap_uart_state *uart)
616 /* Needed to enable UART clocks when built without CONFIG_PM */
617 omap_uart_enable_clocks(uart);
619 #define DEV_CREATE_FILE(dev, attr)
620 #endif /* CONFIG_PM */
622 #ifndef CONFIG_SERIAL_OMAP
624 * Override the default 8250 read handler: mem_serial_in()
625 * Empty RX fifo read causes an abort on omap3630 and omap4
626 * This function makes sure that an empty rx fifo is not read on these silicons
627 * (OMAP1/2/3430 are not affected)
629 static unsigned int serial_in_override(struct uart_port *up, int offset)
631 if (UART_RX == offset) {
633 lsr = __serial_read_reg(up, UART_LSR);
634 if (!(lsr & UART_LSR_DR))
638 return __serial_read_reg(up, offset);
641 static void serial_out_override(struct uart_port *up, int offset, int value)
643 unsigned int status, tmout = 10000;
645 status = __serial_read_reg(up, UART_LSR);
646 while (!(status & UART_LSR_THRE)) {
647 /* Wait up to 10ms for the character(s) to be sent. */
651 status = __serial_read_reg(up, UART_LSR);
653 __serial_write_reg(up, offset, value);
657 void __init omap_serial_early_init(void)
662 char oh_name[MAX_UART_HWMOD_NAME_LEN];
663 struct omap_hwmod *oh;
664 struct omap_uart_state *uart;
666 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
668 oh = omap_hwmod_lookup(oh_name);
672 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
678 list_add_tail(&uart->node, &uart_list);
682 * NOTE: omap_hwmod_init() has not yet been called,
683 * so no hwmod functions will work yet.
687 * During UART early init, device need to be probed
688 * to determine SoC specific init before omap_device
689 * is ready. Therefore, don't allow idle here
691 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
696 * omap_serial_init_port() - initialize single serial port
697 * @port: serial port number (0-3)
699 * This function initialies serial driver for given @port only.
700 * Platforms can call this function instead of omap_serial_init()
701 * if they don't plan to use all available UARTs as serial ports.
703 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
704 * use only one of the two.
706 void __init omap_serial_init_port(int port)
708 struct omap_uart_state *uart;
709 struct omap_hwmod *oh;
710 struct omap_device *od;
714 #ifndef CONFIG_SERIAL_OMAP
715 struct plat_serial8250_port ports[2] = {
719 struct plat_serial8250_port *p = &ports[0];
721 struct omap_uart_port_info omap_up;
724 if (WARN_ON(port < 0))
726 if (WARN_ON(port >= num_uarts))
729 list_for_each_entry(uart, &uart_list, node)
730 if (port == uart->num)
734 uart->dma_enabled = 0;
735 #ifndef CONFIG_SERIAL_OMAP
739 * !! 8250 driver does not use standard IORESOURCE* It
740 * has it's own custom pdata that can be taken from
741 * the hwmod resource data. But, this needs to be
742 * done after the build.
744 * ?? does it have to be done before the register ??
745 * YES, because platform_device_data_add() copies
746 * pdata, it does not use a pointer.
748 p->flags = UPF_BOOT_AUTOCONF;
749 p->iotype = UPIO_MEM;
751 p->uartclk = OMAP24XX_BASE_BAUD * 16;
752 p->irq = oh->mpu_irqs[0].irq;
753 p->mapbase = oh->slaves[0]->addr->pa_start;
754 p->membase = omap_hwmod_get_mpu_rt_va(oh);
755 p->irqflags = IRQF_SHARED;
756 p->private_data = uart;
759 * omap44xx: Never read empty UART fifo
760 * omap3xxx: Never read empty UART fifo on UARTs
763 uart->regshift = p->regshift;
764 uart->membase = p->membase;
765 if (cpu_is_omap44xx())
766 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
767 else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
768 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
769 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
771 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
772 p->serial_in = serial_in_override;
773 p->serial_out = serial_out_override;
777 pdata_size = 2 * sizeof(struct plat_serial8250_port);
782 omap_up.dma_enabled = uart->dma_enabled;
783 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
784 omap_up.mapbase = oh->slaves[0]->addr->pa_start;
785 omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
786 omap_up.irqflags = IRQF_SHARED;
787 omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
790 pdata_size = sizeof(struct omap_uart_port_info);
796 od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
798 ARRAY_SIZE(omap_uart_latency), false);
799 WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
802 uart->irq = oh->mpu_irqs[0].irq;
804 uart->mapbase = oh->slaves[0]->addr->pa_start;
805 uart->membase = omap_hwmod_get_mpu_rt_va(oh);
806 uart->pdev = &od->pdev;
811 * Because of early UART probing, UART did not get idled
812 * on init. Now that omap_device is ready, ensure full idle
813 * before doing omap_device_enable().
815 omap_hwmod_idle(uart->oh);
817 omap_device_enable(uart->pdev);
818 omap_uart_idle_init(uart);
819 omap_uart_reset(uart);
820 omap_hwmod_enable_wakeup(uart->oh);
821 omap_device_idle(uart->pdev);
824 * Need to block sleep long enough for interrupt driven
825 * driver to start. Console driver is in polling mode
826 * so device needs to be kept enabled while polling driver
830 uart->timeout = (30 * HZ);
831 omap_uart_block_sleep(uart);
832 uart->timeout = DEFAULT_TIMEOUT;
834 if ((cpu_is_omap34xx() && uart->padconf) ||
835 (uart->wk_en && uart->wk_mask)) {
836 device_init_wakeup(&od->pdev.dev, true);
837 DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
840 /* Enable the MDR1 errata for OMAP3 */
841 if (cpu_is_omap34xx())
842 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
846 * omap_serial_init() - intialize all supported serial ports
848 * Initializes all available UARTs as serial ports. Platforms
849 * can call this function when they want to have default behaviour
850 * for serial ports (e.g initialize them all as serial ports).
852 void __init omap_serial_init(void)
854 struct omap_uart_state *uart;
856 list_for_each_entry(uart, &uart_list, node)
857 omap_serial_init_port(uart->num);