2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
27 #include <mach/common.h>
28 #include <mach/board.h>
29 #include <mach/clock.h>
30 #include <mach/control.h>
34 #include "prm-regbits-34xx.h"
36 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
38 #define DEFAULT_TIMEOUT (5 * HZ)
40 struct omap_uart_state {
43 struct timer_list timer;
55 struct plat_serial8250_port *p;
56 struct list_head node;
57 struct platform_device pdev;
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
62 /* Registers to be saved/restored for OFF-mode */
72 static LIST_HEAD(uart_list);
74 static struct plat_serial8250_port serial_platform_data0[] = {
76 .membase = IO_ADDRESS(OMAP_UART1_BASE),
77 .mapbase = OMAP_UART1_BASE,
79 .flags = UPF_BOOT_AUTOCONF,
82 .uartclk = OMAP24XX_BASE_BAUD * 16,
88 static struct plat_serial8250_port serial_platform_data1[] = {
90 .membase = IO_ADDRESS(OMAP_UART2_BASE),
91 .mapbase = OMAP_UART2_BASE,
93 .flags = UPF_BOOT_AUTOCONF,
96 .uartclk = OMAP24XX_BASE_BAUD * 16,
102 static struct plat_serial8250_port serial_platform_data2[] = {
104 .membase = IO_ADDRESS(OMAP_UART3_BASE),
105 .mapbase = OMAP_UART3_BASE,
107 .flags = UPF_BOOT_AUTOCONF,
110 .uartclk = OMAP24XX_BASE_BAUD * 16,
112 #ifdef CONFIG_ARCH_OMAP4
113 .membase = IO_ADDRESS(OMAP_UART4_BASE),
114 .mapbase = OMAP_UART4_BASE,
116 .flags = UPF_BOOT_AUTOCONF,
119 .uartclk = OMAP24XX_BASE_BAUD * 16,
126 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
129 offset <<= up->regshift;
130 return (unsigned int)__raw_readb(up->membase + offset);
133 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
136 offset <<= p->regshift;
137 __raw_writeb(value, p->membase + offset);
141 * Internal UARTs need to be initialized for the 8250 autoconfig to work
142 * properly. Note that the TX watermark initialization may not be needed
143 * once the 8250.c watermark handling code is merged.
145 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
147 struct plat_serial8250_port *p = uart->p;
149 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
150 serial_write_reg(p, UART_OMAP_SCR, 0x08);
151 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
152 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
155 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
157 static int enable_off_mode; /* to be removed by full off-mode patches */
159 static void omap_uart_save_context(struct omap_uart_state *uart)
162 struct plat_serial8250_port *p = uart->p;
164 if (!enable_off_mode)
167 lcr = serial_read_reg(p, UART_LCR);
168 serial_write_reg(p, UART_LCR, 0xBF);
169 uart->dll = serial_read_reg(p, UART_DLL);
170 uart->dlh = serial_read_reg(p, UART_DLM);
171 serial_write_reg(p, UART_LCR, lcr);
172 uart->ier = serial_read_reg(p, UART_IER);
173 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
174 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
175 uart->wer = serial_read_reg(p, UART_OMAP_WER);
177 uart->context_valid = 1;
180 static void omap_uart_restore_context(struct omap_uart_state *uart)
183 struct plat_serial8250_port *p = uart->p;
185 if (!enable_off_mode)
188 if (!uart->context_valid)
191 uart->context_valid = 0;
193 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
194 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
195 efr = serial_read_reg(p, UART_EFR);
196 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
197 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
198 serial_write_reg(p, UART_IER, 0x0);
199 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
200 serial_write_reg(p, UART_DLL, uart->dll);
201 serial_write_reg(p, UART_DLM, uart->dlh);
202 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
203 serial_write_reg(p, UART_IER, uart->ier);
204 serial_write_reg(p, UART_FCR, 0xA1);
205 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
206 serial_write_reg(p, UART_EFR, efr);
207 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
208 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
209 serial_write_reg(p, UART_OMAP_WER, uart->wer);
210 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
211 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
214 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
215 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
216 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
218 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
223 clk_enable(uart->ick);
224 clk_enable(uart->fck);
226 omap_uart_restore_context(uart);
231 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
236 omap_uart_save_context(uart);
238 clk_disable(uart->ick);
239 clk_disable(uart->fck);
242 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
244 /* Set wake-enable bit */
245 if (uart->wk_en && uart->wk_mask) {
246 u32 v = __raw_readl(uart->wk_en);
248 __raw_writel(v, uart->wk_en);
251 /* Ensure IOPAD wake-enables are set */
252 if (cpu_is_omap34xx() && uart->padconf) {
253 u16 v = omap_ctrl_readw(uart->padconf);
254 v |= OMAP3_PADCONF_WAKEUPENABLE0;
255 omap_ctrl_writew(v, uart->padconf);
259 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
261 /* Clear wake-enable bit */
262 if (uart->wk_en && uart->wk_mask) {
263 u32 v = __raw_readl(uart->wk_en);
265 __raw_writel(v, uart->wk_en);
268 /* Ensure IOPAD wake-enables are cleared */
269 if (cpu_is_omap34xx() && uart->padconf) {
270 u16 v = omap_ctrl_readw(uart->padconf);
271 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
272 omap_ctrl_writew(v, uart->padconf);
276 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
279 struct plat_serial8250_port *p = uart->p;
282 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
288 serial_write_reg(p, UART_OMAP_SYSC, sysc);
291 static void omap_uart_block_sleep(struct omap_uart_state *uart)
293 omap_uart_enable_clocks(uart);
295 omap_uart_smart_idle_enable(uart, 0);
298 mod_timer(&uart->timer, jiffies + uart->timeout);
300 del_timer(&uart->timer);
303 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
305 if (device_may_wakeup(&uart->pdev.dev))
306 omap_uart_enable_wakeup(uart);
308 omap_uart_disable_wakeup(uart);
313 omap_uart_smart_idle_enable(uart, 1);
315 del_timer(&uart->timer);
318 static void omap_uart_idle_timer(unsigned long data)
320 struct omap_uart_state *uart = (struct omap_uart_state *)data;
322 omap_uart_allow_sleep(uart);
325 void omap_uart_prepare_idle(int num)
327 struct omap_uart_state *uart;
329 list_for_each_entry(uart, &uart_list, node) {
330 if (num == uart->num && uart->can_sleep) {
331 omap_uart_disable_clocks(uart);
337 void omap_uart_resume_idle(int num)
339 struct omap_uart_state *uart;
341 list_for_each_entry(uart, &uart_list, node) {
342 if (num == uart->num) {
343 omap_uart_enable_clocks(uart);
345 /* Check for IO pad wakeup */
346 if (cpu_is_omap34xx() && uart->padconf) {
347 u16 p = omap_ctrl_readw(uart->padconf);
349 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
350 omap_uart_block_sleep(uart);
353 /* Check for normal UART wakeup */
354 if (__raw_readl(uart->wk_st) & uart->wk_mask)
355 omap_uart_block_sleep(uart);
361 void omap_uart_prepare_suspend(void)
363 struct omap_uart_state *uart;
365 list_for_each_entry(uart, &uart_list, node) {
366 omap_uart_allow_sleep(uart);
370 int omap_uart_can_sleep(void)
372 struct omap_uart_state *uart;
375 list_for_each_entry(uart, &uart_list, node) {
379 if (!uart->can_sleep) {
384 /* This UART can now safely sleep. */
385 omap_uart_allow_sleep(uart);
392 * omap_uart_interrupt()
394 * This handler is used only to detect that *any* UART interrupt has
395 * occurred. It does _nothing_ to handle the interrupt. Rather,
396 * any UART interrupt will trigger the inactivity timer so the
397 * UART will not idle or sleep for its timeout period.
400 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
402 struct omap_uart_state *uart = dev_id;
404 omap_uart_block_sleep(uart);
409 static void omap_uart_idle_init(struct omap_uart_state *uart)
411 struct plat_serial8250_port *p = uart->p;
415 uart->timeout = DEFAULT_TIMEOUT;
416 setup_timer(&uart->timer, omap_uart_idle_timer,
417 (unsigned long) uart);
418 mod_timer(&uart->timer, jiffies + uart->timeout);
419 omap_uart_smart_idle_enable(uart, 0);
421 if (cpu_is_omap34xx()) {
422 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
426 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
427 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
430 wk_mask = OMAP3430_ST_UART1_MASK;
434 wk_mask = OMAP3430_ST_UART2_MASK;
438 wk_mask = OMAP3430_ST_UART3_MASK;
442 uart->wk_mask = wk_mask;
443 uart->padconf = padconf;
444 } else if (cpu_is_omap24xx()) {
447 if (cpu_is_omap2430()) {
448 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
449 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
450 } else if (cpu_is_omap2420()) {
451 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
452 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
456 wk_mask = OMAP24XX_ST_UART1_MASK;
459 wk_mask = OMAP24XX_ST_UART2_MASK;
462 wk_mask = OMAP24XX_ST_UART3_MASK;
465 uart->wk_mask = wk_mask;
473 p->flags |= UPF_SHARE_IRQ;
474 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
475 "serial idle", (void *)uart);
479 void omap_uart_enable_irqs(int enable)
482 struct omap_uart_state *uart;
484 list_for_each_entry(uart, &uart_list, node) {
486 ret = request_irq(uart->p->irq, omap_uart_interrupt,
487 IRQF_SHARED, "serial idle", (void *)uart);
489 free_irq(uart->p->irq, (void *)uart);
493 static ssize_t sleep_timeout_show(struct device *dev,
494 struct device_attribute *attr,
497 struct platform_device *pdev = container_of(dev,
498 struct platform_device, dev);
499 struct omap_uart_state *uart = container_of(pdev,
500 struct omap_uart_state, pdev);
502 return sprintf(buf, "%u\n", uart->timeout / HZ);
505 static ssize_t sleep_timeout_store(struct device *dev,
506 struct device_attribute *attr,
507 const char *buf, size_t n)
509 struct platform_device *pdev = container_of(dev,
510 struct platform_device, dev);
511 struct omap_uart_state *uart = container_of(pdev,
512 struct omap_uart_state, pdev);
515 if (sscanf(buf, "%u", &value) != 1) {
516 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
520 uart->timeout = value * HZ;
522 mod_timer(&uart->timer, jiffies + uart->timeout);
524 /* A zero value means disable timeout feature */
525 omap_uart_block_sleep(uart);
530 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
531 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
533 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
534 #define DEV_CREATE_FILE(dev, attr)
535 #endif /* CONFIG_PM */
537 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
540 .name = "serial8250",
541 .id = PLAT8250_DEV_PLATFORM,
543 .platform_data = serial_platform_data0,
548 .name = "serial8250",
549 .id = PLAT8250_DEV_PLATFORM1,
551 .platform_data = serial_platform_data1,
556 .name = "serial8250",
557 .id = PLAT8250_DEV_PLATFORM2,
559 .platform_data = serial_platform_data2,
565 void __init omap_serial_init(void)
568 const struct omap_uart_config *info;
572 * Make sure the serial ports are muxed on at this point.
573 * You have to mux them off in device drivers later on
577 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
582 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
583 struct omap_uart_state *uart = &omap_uart[i];
584 struct platform_device *pdev = &uart->pdev;
585 struct device *dev = &pdev->dev;
586 struct plat_serial8250_port *p = dev->platform_data;
588 if (!(info->enabled_uarts & (1 << i))) {
594 sprintf(name, "uart%d_ick", i+1);
595 uart->ick = clk_get(NULL, name);
596 if (IS_ERR(uart->ick)) {
597 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
601 sprintf(name, "uart%d_fck", i+1);
602 uart->fck = clk_get(NULL, name);
603 if (IS_ERR(uart->fck)) {
604 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
608 if (!uart->ick || !uart->fck)
612 p->private_data = uart;
614 list_add_tail(&uart->node, &uart_list);
616 if (cpu_is_omap44xx())
619 omap_uart_enable_clocks(uart);
620 omap_uart_reset(uart);
621 omap_uart_idle_init(uart);
623 if (WARN_ON(platform_device_register(pdev)))
625 if ((cpu_is_omap34xx() && uart->padconf) ||
626 (uart->wk_en && uart->wk_mask)) {
627 device_init_wakeup(dev, true);
628 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);