2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
27 #include <mach/common.h>
28 #include <mach/board.h>
29 #include <mach/clock.h>
30 #include <mach/control.h>
34 #include "prm-regbits-34xx.h"
36 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
38 #define DEFAULT_TIMEOUT (5 * HZ)
40 struct omap_uart_state {
43 struct timer_list timer;
55 struct plat_serial8250_port *p;
56 struct list_head node;
57 struct platform_device pdev;
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
62 /* Registers to be saved/restored for OFF-mode */
72 static LIST_HEAD(uart_list);
74 static struct plat_serial8250_port serial_platform_data0[] = {
76 .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
77 .mapbase = OMAP_UART1_BASE,
79 .flags = UPF_BOOT_AUTOCONF,
82 .uartclk = OMAP24XX_BASE_BAUD * 16,
88 static struct plat_serial8250_port serial_platform_data1[] = {
90 .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
91 .mapbase = OMAP_UART2_BASE,
93 .flags = UPF_BOOT_AUTOCONF,
96 .uartclk = OMAP24XX_BASE_BAUD * 16,
102 static struct plat_serial8250_port serial_platform_data2[] = {
104 .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
105 .mapbase = OMAP_UART3_BASE,
107 .flags = UPF_BOOT_AUTOCONF,
110 .uartclk = OMAP24XX_BASE_BAUD * 16,
112 #ifdef CONFIG_ARCH_OMAP4
113 .membase = IO_ADDRESS(OMAP_UART4_BASE),
114 .mapbase = OMAP_UART4_BASE,
116 .flags = UPF_BOOT_AUTOCONF,
119 .uartclk = OMAP24XX_BASE_BAUD * 16,
126 #ifdef CONFIG_ARCH_OMAP4
127 static struct plat_serial8250_port serial_platform_data3[] = {
129 .membase = IO_ADDRESS(OMAP_UART4_BASE),
130 .mapbase = OMAP_UART4_BASE,
132 .flags = UPF_BOOT_AUTOCONF,
135 .uartclk = OMAP24XX_BASE_BAUD * 16,
141 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
144 offset <<= up->regshift;
145 return (unsigned int)__raw_readb(up->membase + offset);
148 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
151 offset <<= p->regshift;
152 __raw_writeb(value, p->membase + offset);
156 * Internal UARTs need to be initialized for the 8250 autoconfig to work
157 * properly. Note that the TX watermark initialization may not be needed
158 * once the 8250.c watermark handling code is merged.
160 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
162 struct plat_serial8250_port *p = uart->p;
164 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
165 serial_write_reg(p, UART_OMAP_SCR, 0x08);
166 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
167 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
170 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
172 static int enable_off_mode; /* to be removed by full off-mode patches */
174 static void omap_uart_save_context(struct omap_uart_state *uart)
177 struct plat_serial8250_port *p = uart->p;
179 if (!enable_off_mode)
182 lcr = serial_read_reg(p, UART_LCR);
183 serial_write_reg(p, UART_LCR, 0xBF);
184 uart->dll = serial_read_reg(p, UART_DLL);
185 uart->dlh = serial_read_reg(p, UART_DLM);
186 serial_write_reg(p, UART_LCR, lcr);
187 uart->ier = serial_read_reg(p, UART_IER);
188 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
189 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
190 uart->wer = serial_read_reg(p, UART_OMAP_WER);
192 uart->context_valid = 1;
195 static void omap_uart_restore_context(struct omap_uart_state *uart)
198 struct plat_serial8250_port *p = uart->p;
200 if (!enable_off_mode)
203 if (!uart->context_valid)
206 uart->context_valid = 0;
208 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
209 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
210 efr = serial_read_reg(p, UART_EFR);
211 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
212 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
213 serial_write_reg(p, UART_IER, 0x0);
214 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
215 serial_write_reg(p, UART_DLL, uart->dll);
216 serial_write_reg(p, UART_DLM, uart->dlh);
217 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
218 serial_write_reg(p, UART_IER, uart->ier);
219 serial_write_reg(p, UART_FCR, 0xA1);
220 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
221 serial_write_reg(p, UART_EFR, efr);
222 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
223 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
224 serial_write_reg(p, UART_OMAP_WER, uart->wer);
225 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
226 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
229 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
230 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
231 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
233 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
238 clk_enable(uart->ick);
239 clk_enable(uart->fck);
241 omap_uart_restore_context(uart);
246 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
251 omap_uart_save_context(uart);
253 clk_disable(uart->ick);
254 clk_disable(uart->fck);
257 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
259 /* Set wake-enable bit */
260 if (uart->wk_en && uart->wk_mask) {
261 u32 v = __raw_readl(uart->wk_en);
263 __raw_writel(v, uart->wk_en);
266 /* Ensure IOPAD wake-enables are set */
267 if (cpu_is_omap34xx() && uart->padconf) {
268 u16 v = omap_ctrl_readw(uart->padconf);
269 v |= OMAP3_PADCONF_WAKEUPENABLE0;
270 omap_ctrl_writew(v, uart->padconf);
274 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
276 /* Clear wake-enable bit */
277 if (uart->wk_en && uart->wk_mask) {
278 u32 v = __raw_readl(uart->wk_en);
280 __raw_writel(v, uart->wk_en);
283 /* Ensure IOPAD wake-enables are cleared */
284 if (cpu_is_omap34xx() && uart->padconf) {
285 u16 v = omap_ctrl_readw(uart->padconf);
286 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
287 omap_ctrl_writew(v, uart->padconf);
291 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
294 struct plat_serial8250_port *p = uart->p;
297 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
303 serial_write_reg(p, UART_OMAP_SYSC, sysc);
306 static void omap_uart_block_sleep(struct omap_uart_state *uart)
308 omap_uart_enable_clocks(uart);
310 omap_uart_smart_idle_enable(uart, 0);
313 mod_timer(&uart->timer, jiffies + uart->timeout);
315 del_timer(&uart->timer);
318 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
320 if (device_may_wakeup(&uart->pdev.dev))
321 omap_uart_enable_wakeup(uart);
323 omap_uart_disable_wakeup(uart);
328 omap_uart_smart_idle_enable(uart, 1);
330 del_timer(&uart->timer);
333 static void omap_uart_idle_timer(unsigned long data)
335 struct omap_uart_state *uart = (struct omap_uart_state *)data;
337 omap_uart_allow_sleep(uart);
340 void omap_uart_prepare_idle(int num)
342 struct omap_uart_state *uart;
344 list_for_each_entry(uart, &uart_list, node) {
345 if (num == uart->num && uart->can_sleep) {
346 omap_uart_disable_clocks(uart);
352 void omap_uart_resume_idle(int num)
354 struct omap_uart_state *uart;
356 list_for_each_entry(uart, &uart_list, node) {
357 if (num == uart->num) {
358 omap_uart_enable_clocks(uart);
360 /* Check for IO pad wakeup */
361 if (cpu_is_omap34xx() && uart->padconf) {
362 u16 p = omap_ctrl_readw(uart->padconf);
364 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
365 omap_uart_block_sleep(uart);
368 /* Check for normal UART wakeup */
369 if (__raw_readl(uart->wk_st) & uart->wk_mask)
370 omap_uart_block_sleep(uart);
376 void omap_uart_prepare_suspend(void)
378 struct omap_uart_state *uart;
380 list_for_each_entry(uart, &uart_list, node) {
381 omap_uart_allow_sleep(uart);
385 int omap_uart_can_sleep(void)
387 struct omap_uart_state *uart;
390 list_for_each_entry(uart, &uart_list, node) {
394 if (!uart->can_sleep) {
399 /* This UART can now safely sleep. */
400 omap_uart_allow_sleep(uart);
407 * omap_uart_interrupt()
409 * This handler is used only to detect that *any* UART interrupt has
410 * occurred. It does _nothing_ to handle the interrupt. Rather,
411 * any UART interrupt will trigger the inactivity timer so the
412 * UART will not idle or sleep for its timeout period.
415 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
417 struct omap_uart_state *uart = dev_id;
419 omap_uart_block_sleep(uart);
424 static void omap_uart_idle_init(struct omap_uart_state *uart)
426 struct plat_serial8250_port *p = uart->p;
430 uart->timeout = DEFAULT_TIMEOUT;
431 setup_timer(&uart->timer, omap_uart_idle_timer,
432 (unsigned long) uart);
433 mod_timer(&uart->timer, jiffies + uart->timeout);
434 omap_uart_smart_idle_enable(uart, 0);
436 if (cpu_is_omap34xx()) {
437 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
441 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
442 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
445 wk_mask = OMAP3430_ST_UART1_MASK;
449 wk_mask = OMAP3430_ST_UART2_MASK;
453 wk_mask = OMAP3430_ST_UART3_MASK;
457 uart->wk_mask = wk_mask;
458 uart->padconf = padconf;
459 } else if (cpu_is_omap24xx()) {
462 if (cpu_is_omap2430()) {
463 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
464 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
465 } else if (cpu_is_omap2420()) {
466 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
467 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
471 wk_mask = OMAP24XX_ST_UART1_MASK;
474 wk_mask = OMAP24XX_ST_UART2_MASK;
477 wk_mask = OMAP24XX_ST_UART3_MASK;
480 uart->wk_mask = wk_mask;
488 p->irqflags |= IRQF_SHARED;
489 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
490 "serial idle", (void *)uart);
494 void omap_uart_enable_irqs(int enable)
497 struct omap_uart_state *uart;
499 list_for_each_entry(uart, &uart_list, node) {
501 ret = request_irq(uart->p->irq, omap_uart_interrupt,
502 IRQF_SHARED, "serial idle", (void *)uart);
504 free_irq(uart->p->irq, (void *)uart);
508 static ssize_t sleep_timeout_show(struct device *dev,
509 struct device_attribute *attr,
512 struct platform_device *pdev = container_of(dev,
513 struct platform_device, dev);
514 struct omap_uart_state *uart = container_of(pdev,
515 struct omap_uart_state, pdev);
517 return sprintf(buf, "%u\n", uart->timeout / HZ);
520 static ssize_t sleep_timeout_store(struct device *dev,
521 struct device_attribute *attr,
522 const char *buf, size_t n)
524 struct platform_device *pdev = container_of(dev,
525 struct platform_device, dev);
526 struct omap_uart_state *uart = container_of(pdev,
527 struct omap_uart_state, pdev);
530 if (sscanf(buf, "%u", &value) != 1) {
531 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
535 uart->timeout = value * HZ;
537 mod_timer(&uart->timer, jiffies + uart->timeout);
539 /* A zero value means disable timeout feature */
540 omap_uart_block_sleep(uart);
545 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
546 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
548 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
549 #define DEV_CREATE_FILE(dev, attr)
550 #endif /* CONFIG_PM */
552 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
555 .name = "serial8250",
556 .id = PLAT8250_DEV_PLATFORM,
558 .platform_data = serial_platform_data0,
563 .name = "serial8250",
564 .id = PLAT8250_DEV_PLATFORM1,
566 .platform_data = serial_platform_data1,
571 .name = "serial8250",
572 .id = PLAT8250_DEV_PLATFORM2,
574 .platform_data = serial_platform_data2,
578 #ifdef CONFIG_ARCH_OMAP4
581 .name = "serial8250",
584 .platform_data = serial_platform_data3,
591 void __init omap_serial_early_init(void)
597 * Make sure the serial ports are muxed on at this point.
598 * You have to mux them off in device drivers later on
602 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
603 struct omap_uart_state *uart = &omap_uart[i];
604 struct platform_device *pdev = &uart->pdev;
605 struct device *dev = &pdev->dev;
606 struct plat_serial8250_port *p = dev->platform_data;
608 sprintf(name, "uart%d_ick", i+1);
609 uart->ick = clk_get(NULL, name);
610 if (IS_ERR(uart->ick)) {
611 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
615 sprintf(name, "uart%d_fck", i+1);
616 uart->fck = clk_get(NULL, name);
617 if (IS_ERR(uart->fck)) {
618 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
622 /* FIXME: Remove this once the clkdev is ready */
623 if (!cpu_is_omap44xx()) {
624 if (!uart->ick || !uart->fck)
629 p->private_data = uart;
631 list_add_tail(&uart->node, &uart_list);
633 if (cpu_is_omap44xx())
636 omap_uart_enable_clocks(uart);
640 void __init omap_serial_init(void)
644 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
645 struct omap_uart_state *uart = &omap_uart[i];
646 struct platform_device *pdev = &uart->pdev;
647 struct device *dev = &pdev->dev;
649 omap_uart_reset(uart);
650 omap_uart_idle_init(uart);
652 if (WARN_ON(platform_device_register(pdev)))
654 if ((cpu_is_omap34xx() && uart->padconf) ||
655 (uart->wk_en && uart->wk_mask)) {
656 device_init_wakeup(dev, true);
657 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);