2 * linux/arch/arm/mach-omap3/sram.S
4 * Omap3 specific functions that need to be run in internal SRAM
6 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
9 * Rajendra Nayak <rnayak@ti.com>
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <linux/linkage.h>
30 #include <asm/assembler.h>
32 #include <mach/hardware.h>
36 #include "cm2xxx_3xxx.h"
39 * This file needs be built unconditionally as ARM to interoperate correctly
40 * with non-Thumb-2-capable firmware.
47 #define SDRC_NO_UNLOCK_DLL 0x0
48 #define SDRC_UNLOCK_DLL 0x1
50 /* SDRC_DLLA_CTRL bit settings */
51 #define FIXEDDELAY_SHIFT 24
52 #define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
53 #define DLLIDLE_MASK 0x4
56 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
57 * FIXEDDELAY should be initialized to 0xf. This apparently was
58 * empirically determined during process testing, so no derivation
61 #define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
63 /* SDRC_DLLA_STATUS bit settings */
64 #define LOCKSTATUS_MASK 0x4
66 /* SDRC_POWER bit settings */
67 #define SRFRONIDLEREQ_MASK 0x40
69 /* CM_IDLEST1_CORE bit settings */
70 #define ST_SDRC_MASK 0x2
72 /* CM_ICLKEN1_CORE bit settings */
73 #define EN_SDRC_MASK 0x2
75 /* CM_CLKSEL1_PLL bit settings */
76 #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
79 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
81 * Params passed in registers:
82 * r0 = new M2 divider setting (only 1 and 2 supported right now)
83 * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
85 * r2 = number of MPU cycles to wait for SDRC to stabilize after
86 * reprogramming the SDRC when switching to a slower MPU speed
87 * r3 = increasing SDRC rate? (1 = yes, 0 = no)
89 * Params passed via the stack. The needed params will be copied in SRAM
90 * before use by the code in SRAM (SDRAM is not accessible during SDRC
92 * new SDRC_RFR_CTRL_0 register contents
93 * new SDRC_ACTIM_CTRL_A_0 register contents
94 * new SDRC_ACTIM_CTRL_B_0 register contents
95 * new SDRC_MR_0 register value
96 * new SDRC_RFR_CTRL_1 register contents
97 * new SDRC_ACTIM_CTRL_A_1 register contents
98 * new SDRC_ACTIM_CTRL_B_1 register contents
99 * new SDRC_MR_1 register value
101 * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
102 * the SDRC CS1 registers
104 * NOTE: This code no longer attempts to program the SDRC AC timing and MR
105 * registers. This is because the code currently cannot ensure that all
106 * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
107 * SDRAM when the registers are written. If the registers are changed while
108 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
109 * may enter an unpredictable state. In the future, the intent is to
110 * re-enable this code in cases where we can ensure that no initiators are
111 * touching the SDRAM. Until that time, users who know that their use case
112 * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
115 * Richard Woodruff notes that any changes to this code must be carefully
116 * audited and tested to ensure that they don't cause a TLB miss while
117 * the SDRAM is inaccessible. Such a situation will crash the system
118 * since it will cause the ARM MMU to attempt to walk the page tables.
119 * These crashes may be intermittent.
122 ENTRY(omap3_sram_configure_core_dpll)
123 stmfd sp!, {r1-r12, lr} @ store regs to stack
125 @ pull the extra args off the stack
126 @ and store them in SRAM
129 * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
130 * in Thumb-2: use a r7 as a base instead.
131 * Be careful not to clobber r7 when maintaing this file.
133 THUMB( adr r7, omap3_sram_configure_core_dpll )
134 .macro strtext Rt:req, label:req
135 ARM( str \Rt, \label )
136 THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] )
140 strtext r4, omap_sdrc_rfr_ctrl_0_val
142 strtext r4, omap_sdrc_actim_ctrl_a_0_val
144 strtext r4, omap_sdrc_actim_ctrl_b_0_val
146 strtext r4, omap_sdrc_mr_0_val
148 strtext r4, omap_sdrc_rfr_ctrl_1_val
149 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
150 beq skip_cs1_params @ do not use cs1 params
152 strtext r4, omap_sdrc_actim_ctrl_a_1_val
154 strtext r4, omap_sdrc_actim_ctrl_b_1_val
156 strtext r4, omap_sdrc_mr_1_val
158 mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
159 bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
160 mcr p15, 0, r10, c1, c0, 0 @ write ctrl register
161 dsb @ flush buffered writes to interconnect
162 isb @ prevent speculative exec past here
163 cmp r3, #1 @ if increasing SDRC clk rate,
164 bleq configure_sdrc @ program the SDRC regs early (for RFR)
165 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
168 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
169 bl configure_core_dpll @ change the DPLL3 M2 divider
171 bl wait_clk_stable @ wait for SDRC to stabilize
172 bl enable_sdrc @ take SDRC out of idle
173 cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
176 cmp r3, #1 @ if increasing SDRC clk rate,
177 beq return_to_sdram @ return to SDRAM code, otherwise,
178 bl configure_sdrc @ reprogram SDRC regs now
180 mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
181 isb @ prevent speculative exec past here
182 mov r0, #0 @ return value
183 ldmfd sp!, {r1-r12, pc} @ restore regs and return
185 ldr r11, omap3_sdrc_dlla_ctrl
187 bic r12, r12, #FIXEDDELAY_MASK
188 orr r12, r12, #FIXEDDELAY_DEFAULT
189 orr r12, r12, #DLLIDLE_MASK
190 str r12, [r11] @ (no OCP barrier needed)
193 ldr r11, omap3_sdrc_dlla_ctrl
195 bic r12, r12, #DLLIDLE_MASK
196 str r12, [r11] @ (no OCP barrier needed)
198 sdram_in_selfrefresh:
199 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
200 ldr r12, [r11] @ read the contents of SDRC_POWER
201 mov r9, r12 @ keep a copy of SDRC_POWER bits
202 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
203 str r12, [r11] @ write back to SDRC_POWER register
204 ldr r12, [r11] @ posted-write barrier for SDRC
206 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
208 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
211 ldr r11, omap3_cm_idlest1_core
213 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
214 cmp r12, #ST_SDRC_MASK
218 ldr r11, omap3_cm_clksel1_pll
220 ldr r10, core_m2_mask_val @ modify m2 for core dpll
222 orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
224 ldr r12, [r11] @ posted-write barrier for CM
231 ldr r11, omap3_cm_iclken1_core
233 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
236 ldr r11, omap3_cm_idlest1_core
238 and r12, r12, #ST_SDRC_MASK
241 restore_sdrc_power_val:
242 ldr r11, omap3_sdrc_power
243 str r9, [r11] @ restore SDRC_POWER, no barrier needed
246 ldr r11, omap3_sdrc_dlla_status
248 and r12, r12, #LOCKSTATUS_MASK
249 cmp r12, #LOCKSTATUS_MASK
253 ldr r11, omap3_sdrc_dlla_status
255 and r12, r12, #LOCKSTATUS_MASK
260 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
261 ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
262 str r12, [r11] @ store
263 #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
264 ldr r12, omap_sdrc_actim_ctrl_a_0_val
265 ldr r11, omap3_sdrc_actim_ctrl_a_0
267 ldr r12, omap_sdrc_actim_ctrl_b_0_val
268 ldr r11, omap3_sdrc_actim_ctrl_b_0
270 ldr r12, omap_sdrc_mr_0_val
271 ldr r11, omap3_sdrc_mr_0
274 ldr r12, omap_sdrc_rfr_ctrl_1_val
275 cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
276 beq skip_cs1_prog @ do not program cs1 params
277 ldr r11, omap3_sdrc_rfr_ctrl_1
279 #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
280 ldr r12, omap_sdrc_actim_ctrl_a_1_val
281 ldr r11, omap3_sdrc_actim_ctrl_a_1
283 ldr r12, omap_sdrc_actim_ctrl_b_1_val
284 ldr r11, omap3_sdrc_actim_ctrl_b_1
286 ldr r12, omap_sdrc_mr_1_val
287 ldr r11, omap3_sdrc_mr_1
291 ldr r12, [r11] @ posted-write barrier for SDRC
296 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
297 omap3_cm_clksel1_pll:
298 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
299 omap3_cm_idlest1_core:
300 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
301 omap3_cm_iclken1_core:
302 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
304 omap3_sdrc_rfr_ctrl_0:
305 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
306 omap3_sdrc_rfr_ctrl_1:
307 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
308 omap3_sdrc_actim_ctrl_a_0:
309 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
310 omap3_sdrc_actim_ctrl_a_1:
311 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
312 omap3_sdrc_actim_ctrl_b_0:
313 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
314 omap3_sdrc_actim_ctrl_b_1:
315 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
317 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
319 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
320 omap_sdrc_rfr_ctrl_0_val:
322 omap_sdrc_rfr_ctrl_1_val:
324 omap_sdrc_actim_ctrl_a_0_val:
326 omap_sdrc_actim_ctrl_a_1_val:
328 omap_sdrc_actim_ctrl_b_0_val:
330 omap_sdrc_actim_ctrl_b_1_val:
337 omap3_sdrc_dlla_status:
338 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
339 omap3_sdrc_dlla_ctrl:
340 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
343 ENDPROC(omap3_sram_configure_core_dpll)
345 ENTRY(omap3_sram_configure_core_dpll_sz)
346 .word . - omap3_sram_configure_core_dpll