2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
44 #include <linux/sched_clock.h>
46 #include <asm/mach/time.h>
47 #include <asm/smp_twd.h>
49 #include "omap_hwmod.h"
50 #include "omap_device.h"
51 #include <plat/counter-32k.h>
52 #include <plat/dmtimer.h>
58 #include "powerdomain.h"
59 #include "omap-secure.h"
61 #define REALTIME_COUNTER_BASE 0x48243200
62 #define INCREMENTER_NUMERATOR_OFFSET 0x10
63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
64 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
68 static struct omap_dm_timer clkev;
69 static struct clock_event_device clockevent_gpt;
71 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
72 static unsigned long arch_timer_freq;
74 void set_cntfreq(void)
76 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
82 struct clock_event_device *evt = &clockevent_gpt;
84 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
86 evt->event_handler(evt);
90 static struct irqaction omap2_gp_timer_irq = {
92 .flags = IRQF_TIMER | IRQF_IRQPOLL,
93 .handler = omap2_gp_timer_interrupt,
96 static int omap2_gp_timer_set_next_event(unsigned long cycles,
97 struct clock_event_device *evt)
99 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
100 0xffffffff - cycles, OMAP_TIMER_POSTED);
105 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
107 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
111 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
115 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
117 period = clkev.rate / HZ;
119 /* Looks like we need to first set the load value separately */
120 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
122 __omap_dm_timer_load_start(&clkev,
123 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
124 0xffffffff - period, OMAP_TIMER_POSTED);
128 static struct clock_event_device clockevent_gpt = {
129 .features = CLOCK_EVT_FEAT_PERIODIC |
130 CLOCK_EVT_FEAT_ONESHOT,
132 .set_next_event = omap2_gp_timer_set_next_event,
133 .set_state_shutdown = omap2_gp_timer_shutdown,
134 .set_state_periodic = omap2_gp_timer_set_periodic,
135 .set_state_oneshot = omap2_gp_timer_shutdown,
136 .tick_resume = omap2_gp_timer_shutdown,
139 static struct property device_disabled = {
141 .length = sizeof("disabled"),
145 static const struct of_device_id omap_timer_match[] __initconst = {
146 { .compatible = "ti,omap2420-timer", },
147 { .compatible = "ti,omap3430-timer", },
148 { .compatible = "ti,omap4430-timer", },
149 { .compatible = "ti,omap5430-timer", },
150 { .compatible = "ti,dm814-timer", },
151 { .compatible = "ti,dm816-timer", },
152 { .compatible = "ti,am335x-timer", },
153 { .compatible = "ti,am335x-timer-1ms", },
158 * omap_get_timer_dt - get a timer using device-tree
159 * @match - device-tree match structure for matching a device type
160 * @property - optional timer property to match
162 * Helper function to get a timer during early boot using device-tree for use
163 * as kernel system timer. Optionally, the property argument can be used to
164 * select a timer with a specific property. Once a timer is found then mark
165 * the timer node in device-tree as disabled, to prevent the kernel from
166 * registering this timer as a platform device and so no one else can use it.
168 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
169 const char *property)
171 struct device_node *np;
173 for_each_matching_node(np, match) {
174 if (!of_device_is_available(np))
177 if (property && !of_get_property(np, property, NULL))
180 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
181 of_get_property(np, "ti,timer-dsp", NULL) ||
182 of_get_property(np, "ti,timer-pwm", NULL) ||
183 of_get_property(np, "ti,timer-secure", NULL)))
186 if (!of_device_is_compatible(np, "ti,omap-counter32k"))
187 of_add_property(np, &device_disabled);
195 * omap_dmtimer_init - initialisation function when device tree is used
197 * For secure OMAP3 devices, timers with device type "timer-secure" cannot
198 * be used by the kernel as they are reserved. Therefore, to prevent the
199 * kernel registering these devices remove them dynamically from the device
202 static void __init omap_dmtimer_init(void)
204 struct device_node *np;
206 if (!cpu_is_omap34xx())
209 /* If we are a secure device, remove any secure timer nodes */
210 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
211 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
217 * omap_dm_timer_get_errata - get errata flags for a timer
219 * Get the timer errata flags that are specific to the OMAP device being used.
221 static u32 __init omap_dm_timer_get_errata(void)
223 if (cpu_is_omap24xx())
226 return OMAP_TIMER_ERRATA_I103_I767;
229 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
230 const char *fck_source,
231 const char *property,
232 const char **timer_name,
235 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
236 const char *oh_name = NULL;
237 struct device_node *np;
238 struct omap_hwmod *oh;
239 struct resource irq, mem;
243 if (of_have_populated_dt()) {
244 np = omap_get_timer_dt(omap_timer_match, property);
248 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
252 timer->irq = irq_of_parse_and_map(np, 0);
256 timer->io_base = of_iomap(np, 0);
260 if (omap_dm_timer_reserve_systimer(timer->id))
263 sprintf(name, "timer%d", timer->id);
267 oh = omap_hwmod_lookup(oh_name);
271 *timer_name = oh->name;
273 if (!of_have_populated_dt()) {
274 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
278 timer->irq = irq.start;
280 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
285 /* Static mapping, never released */
286 timer->io_base = ioremap(mem.start, mem.end - mem.start);
292 /* After the dmtimer is using hwmod these clocks won't be needed */
293 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
294 if (IS_ERR(timer->fclk))
295 return PTR_ERR(timer->fclk);
297 src = clk_get(NULL, fck_source);
301 WARN(clk_set_parent(timer->fclk, src) < 0,
302 "Cannot set timer parent clock, no PLL clock driver?");
306 omap_hwmod_setup_one(oh_name);
307 omap_hwmod_enable(oh);
308 __omap_dm_timer_init_regs(timer);
311 __omap_dm_timer_enable_posted(timer);
313 /* Check that the intended posted configuration matches the actual */
314 if (posted != timer->posted)
317 timer->rate = clk_get_rate(timer->fclk);
323 static void __init omap2_gp_clockevent_init(int gptimer_id,
324 const char *fck_source,
325 const char *property)
329 clkev.id = gptimer_id;
330 clkev.errata = omap_dm_timer_get_errata();
333 * For clock-event timers we never read the timer counter and
334 * so we are not impacted by errata i103 and i767. Therefore,
335 * we can safely ignore this errata for clock-event timers.
337 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
339 res = omap_dm_timer_init_one(&clkev, fck_source, property,
340 &clockevent_gpt.name, OMAP_TIMER_POSTED);
343 omap2_gp_timer_irq.dev_id = &clkev;
344 setup_irq(clkev.irq, &omap2_gp_timer_irq);
346 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
348 clockevent_gpt.cpumask = cpu_possible_mask;
349 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
350 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
351 3, /* Timer internal resynch latency */
354 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
358 /* Clocksource code */
359 static struct omap_dm_timer clksrc;
360 static bool use_gptimer_clksrc __initdata;
365 static cycle_t clocksource_read_cycles(struct clocksource *cs)
367 return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
368 OMAP_TIMER_NONPOSTED);
371 static struct clocksource clocksource_gpt = {
373 .read = clocksource_read_cycles,
374 .mask = CLOCKSOURCE_MASK(32),
375 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
378 static u64 notrace dmtimer_read_sched_clock(void)
381 return __omap_dm_timer_read_counter(&clksrc,
382 OMAP_TIMER_NONPOSTED);
387 static const struct of_device_id omap_counter_match[] __initconst = {
388 { .compatible = "ti,omap-counter32k", },
392 /* Setup free-running counter for clocksource */
393 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
396 struct device_node *np = NULL;
397 struct omap_hwmod *oh;
398 const char *oh_name = "counter_32k";
401 * If device-tree is present, then search the DT blob
402 * to see if the 32kHz counter is supported.
404 if (of_have_populated_dt()) {
405 np = omap_get_timer_dt(omap_counter_match, NULL);
409 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
415 * First check hwmod data is available for sync32k counter
417 oh = omap_hwmod_lookup(oh_name);
418 if (!oh || oh->slaves_cnt == 0)
421 omap_hwmod_setup_one(oh_name);
423 ret = omap_hwmod_enable(oh);
425 pr_warn("%s: failed to enable counter_32k module (%d)\n",
430 if (!of_have_populated_dt()) {
433 vbase = omap_hwmod_get_mpu_rt_va(oh);
435 ret = omap_init_clocksource_32k(vbase);
437 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
445 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
446 const char *fck_source,
447 const char *property)
451 clksrc.id = gptimer_id;
452 clksrc.errata = omap_dm_timer_get_errata();
454 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
455 &clocksource_gpt.name,
456 OMAP_TIMER_NONPOSTED);
459 __omap_dm_timer_load_start(&clksrc,
460 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
461 OMAP_TIMER_NONPOSTED);
462 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
464 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
465 pr_err("Could not register clocksource %s\n",
466 clocksource_gpt.name);
468 pr_info("OMAP clocksource: %s at %lu Hz\n",
469 clocksource_gpt.name, clksrc.rate);
472 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
473 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
474 const char *clksrc_prop, bool gptimer)
478 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
480 /* Enable the use of clocksource="gp_timer" kernel parameter */
481 if (use_gptimer_clksrc || gptimer)
482 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
485 omap2_sync32k_clocksource_init();
488 void __init omap_init_time(void)
490 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
491 2, "timer_sys_ck", NULL, false);
493 if (of_have_populated_dt())
494 clocksource_of_init();
497 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
498 void __init omap3_secure_sync32k_timer_init(void)
500 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
501 2, "timer_sys_ck", NULL, false);
503 #endif /* CONFIG_ARCH_OMAP3 */
505 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
506 void __init omap3_gptimer_timer_init(void)
508 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
509 1, "timer_sys_ck", "ti,timer-alwon", true);
513 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
514 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
515 static void __init omap4_sync32k_timer_init(void)
517 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
518 2, "sys_clkin_ck", NULL, false);
521 void __init omap4_local_timer_init(void)
523 omap4_sync32k_timer_init();
524 clocksource_of_init();
528 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
531 * The realtime counter also called master counter, is a free-running
532 * counter, which is related to real time. It produces the count used
533 * by the CPU local timer peripherals in the MPU cluster. The timer counts
534 * at a rate of 6.144 MHz. Because the device operates on different clocks
535 * in different power modes, the master counter shifts operation between
536 * clocks, adjusting the increment per clock in hardware accordingly to
537 * maintain a constant count rate.
539 static void __init realtime_counter_init(void)
541 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
543 static struct clk *sys_clk;
546 unsigned long long num, den;
548 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
550 pr_err("%s: ioremap failed\n", __func__);
553 sys_clk = clk_get(NULL, "sys_clkin");
554 if (IS_ERR(sys_clk)) {
555 pr_err("%s: failed to get system clock handle\n", __func__);
560 rate = clk_get_rate(sys_clk);
562 if (soc_is_dra7xx()) {
564 * Errata i856 says the 32.768KHz crystal does not start at
565 * power on, so the CPU falls back to an emulated 32KHz clock
566 * based on sysclk / 610 instead. This causes the master counter
567 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
568 * (OR sysclk * 75 / 244)
570 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
571 * Of course any board built without a populated 32.768KHz
572 * crystal would also need this fix even if the CPU is fixed
575 * Either case can be detected by using the two speedselect bits
576 * If they are not 0, then the 32.768KHz clock driving the
577 * coarse counter that corrects the fine counter every time it
578 * ticks is actually rate/610 rather than 32.768KHz and we
579 * should compensate to avoid the 570ppm (at 20MHz, much worse
580 * at other rates) too fast system time.
582 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
583 if (reg & DRA7_SPEEDSELECT_MASK) {
590 /* Numerator/denumerator values refer TRM Realtime Counter section */
618 /* Program it for 38.4 MHz */
625 /* Program numerator and denumerator registers */
626 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
627 NUMERATOR_DENUMERATOR_MASK;
629 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
631 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
632 NUMERATOR_DENUMERATOR_MASK;
634 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
636 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
643 void __init omap5_realtime_timer_init(void)
645 omap4_sync32k_timer_init();
646 realtime_counter_init();
648 clocksource_of_init();
650 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
653 * omap_timer_init - build and register timer device with an
654 * associated timer hwmod
655 * @oh: timer hwmod pointer to be used to build timer device
656 * @user: parameter that can be passed from calling hwmod API
658 * Called by omap_hwmod_for_each_by_class to register each of the timer
659 * devices present in the system. The number of timer devices is known
660 * by parsing through the hwmod database for a given class name. At the
661 * end of function call memory is allocated for timer device and it is
662 * registered to the framework ready to be proved by the driver.
664 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
668 char *name = "omap_timer";
669 struct dmtimer_platform_data *pdata;
670 struct platform_device *pdev;
671 struct omap_timer_capability_dev_attr *timer_dev_attr;
673 pr_debug("%s: %s\n", __func__, oh->name);
675 /* on secure device, do not register secure timer */
676 timer_dev_attr = oh->dev_attr;
677 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
678 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
681 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
683 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
688 * Extract the IDs from name field in hwmod database
689 * and use the same for constructing ids' for the
690 * timer devices. In a way, we are avoiding usage of
691 * static variable witin the function to do the same.
692 * CAUTION: We have to be careful and make sure the
693 * name in hwmod database does not change in which case
694 * we might either make corresponding change here or
695 * switch back static variable mechanism.
697 sscanf(oh->name, "timer%2d", &id);
700 pdata->timer_capability = timer_dev_attr->timer_capability;
702 pdata->timer_errata = omap_dm_timer_get_errata();
703 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
705 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
708 pr_err("%s: Can't build omap_device for %s: %s.\n",
709 __func__, name, oh->name);
719 * omap2_dm_timer_init - top level regular device initialization
721 * Uses dedicated hwmod api to parse through hwmod database for
722 * given class name and then build and register the timer device.
724 static int __init omap2_dm_timer_init(void)
728 /* If dtb is there, the devices will be created dynamically */
729 if (of_have_populated_dt())
732 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
734 pr_err("%s: device registration failed.\n", __func__);
740 omap_arch_initcall(omap2_dm_timer_init);
743 * omap2_override_clocksource - clocksource override with user configuration
745 * Allows user to override default clocksource, using kernel parameter
746 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
748 * Note that, here we are using same standard kernel parameter "clocksource=",
749 * and not introducing any OMAP specific interface.
751 static int __init omap2_override_clocksource(char *str)
756 * For OMAP architecture, we only have two options
757 * - sync_32k (default)
758 * - gp_timer (sys_clk based)
760 if (!strcmp(str, "gp_timer"))
761 use_gptimer_clksrc = true;
765 early_param("clocksource", omap2_override_clocksource);