arch/arm/mach-omap2/vc.c

   1 /*
   2  * OMAP Voltage Controller (VC) interface
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13
  14 #include <plat/cpu.h>
  15
  16 #include "voltage.h"
  17 #include "vc.h"
  18 #include "prm-regbits-34xx.h"
  19 #include "prm-regbits-44xx.h"
  20 #include "prm44xx.h"
  21
  22 /**
  23  * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
  24  * @sa: bit for slave address
  25  * @rav: bit for voltage configuration register
  26  * @rac: bit for command configuration register
  27  * @racen: enable bit for RAC
  28  * @cmd: bit for command value set selection
  29  *
  30  * Channel configuration bits, common for OMAP3+
  31  * OMAP3 register: PRM_VC_CH_CONF
  32  * OMAP4 register: PRM_VC_CFG_CHANNEL
  33  * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
  34  */
  35 struct omap_vc_channel_cfg {
  36         u8 sa;
  37         u8 rav;
  38         u8 rac;
  39         u8 racen;
  40         u8 cmd;
  41 };
  42
  43 static struct omap_vc_channel_cfg vc_default_channel_cfg = {
  44         .sa    = BIT(0),
  45         .rav   = BIT(1),
  46         .rac   = BIT(2),
  47         .racen = BIT(3),
  48         .cmd   = BIT(4),
  49 };
  50
  51 /*
  52  * On OMAP3+, all VC channels have the above default bitfield
  53  * configuration, except the OMAP4 MPU channel.  This appears
  54  * to be a freak accident as every other VC channel has the
  55  * default configuration, thus creating a mutant channel config.
  56  */
  57 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
  58         .sa    = BIT(0),
  59         .rav   = BIT(2),
  60         .rac   = BIT(3),
  61         .racen = BIT(4),
  62         .cmd   = BIT(1),
  63 };
  64
  65 static struct omap_vc_channel_cfg *vc_cfg_bits;
  66 #define CFG_CHANNEL_MASK 0x1f
  67
  68 /**
  69  * omap_vc_config_channel - configure VC channel to PMIC mappings
  70  * @voltdm: pointer to voltagdomain defining the desired VC channel
  71  *
  72  * Configures the VC channel to PMIC mappings for the following
  73  * PMIC settings
  74  * - i2c slave address (SA)
  75  * - voltage configuration address (RAV)
  76  * - command configuration address (RAC) and enable bit (RACEN)
  77  * - command values for ON, ONLP, RET and OFF (CMD)
  78  *
  79  * This function currently only allows flexible configuration of the
  80  * non-default channel.  Starting with OMAP4, there are more than 2
  81  * channels, with one defined as the default (on OMAP4, it's MPU.)
  82  * Only the non-default channel can be configured.
  83  */
  84 static int omap_vc_config_channel(struct voltagedomain *voltdm)
  85 {
  86         struct omap_vc_channel *vc = voltdm->vc;
  87
  88         /*
  89          * For default channel, the only configurable bit is RACEN.
  90          * All others must stay at zero (see function comment above.)
  91          */
  92         if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
  93                 vc->cfg_channel &= vc_cfg_bits->racen;
  94
  95         voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
  96                     vc->cfg_channel << vc->cfg_channel_sa_shift,
  97                     vc->common->cfg_channel_reg);
  98
  99         return 0;
 100 }
 101
 102 /* Voltage scale and accessory APIs */
 103 int omap_vc_pre_scale(struct voltagedomain *voltdm,
 104                       unsigned long target_volt,
 105                       u8 *target_vsel, u8 *current_vsel)
 106 {
 107         struct omap_vc_channel *vc = voltdm->vc;
 108         struct omap_vdd_info *vdd = voltdm->vdd;
 109         struct omap_volt_data *volt_data;
 110         u32 vc_cmdval, vp_errgain_val;
 111
 112         /* Check if sufficient pmic info is available for this vdd */
 113         if (!voltdm->pmic) {
 114                 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
 115                         __func__, voltdm->name);
 116                 return -EINVAL;
 117         }
 118
 119         if (!voltdm->pmic->uv_to_vsel) {
 120                 pr_err("%s: PMIC function to convert voltage in uV to"
 121                         "vsel not registered. Hence unable to scale voltage"
 122                         "for vdd_%s\n", __func__, voltdm->name);
 123                 return -ENODATA;
 124         }
 125
 126         if (!voltdm->read || !voltdm->write) {
 127                 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 128                         __func__, voltdm->name);
 129                 return -EINVAL;
 130         }
 131
 132         /* Get volt_data corresponding to target_volt */
 133         volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
 134         if (IS_ERR(volt_data))
 135                 volt_data = NULL;
 136
 137         *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
 138         *current_vsel = voltdm->pmic->uv_to_vsel(vdd->curr_volt);
 139
 140         /* Setting the ON voltage to the new target voltage */
 141         vc_cmdval = voltdm->read(vc->cmdval_reg);
 142         vc_cmdval &= ~vc->common->cmd_on_mask;
 143         vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
 144         voltdm->write(vc_cmdval, vc->cmdval_reg);
 145
 146         /* Setting vp errorgain based on the voltage */
 147         if (volt_data) {
 148                 vp_errgain_val = voltdm->read(voltdm->vp->vpconfig);
 149                 vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
 150                 vp_errgain_val &= voltdm->vp->common->vpconfig_errorgain_mask;
 151                 vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
 152                         __ffs(voltdm->vp->common->vpconfig_errorgain_mask);
 153                 voltdm->write(vp_errgain_val, voltdm->vp->vpconfig);
 154         }
 155
 156         return 0;
 157 }
 158
 159 void omap_vc_post_scale(struct voltagedomain *voltdm,
 160                         unsigned long target_volt,
 161                         u8 target_vsel, u8 current_vsel)
 162 {
 163         struct omap_vdd_info *vdd = voltdm->vdd;
 164         u32 smps_steps = 0, smps_delay = 0;
 165
 166         smps_steps = abs(target_vsel - current_vsel);
 167         /* SMPS slew rate / step size. 2us added as buffer. */
 168         smps_delay = ((smps_steps * voltdm->pmic->step_size) /
 169                         voltdm->pmic->slew_rate) + 2;
 170         udelay(smps_delay);
 171
 172         vdd->curr_volt = target_volt;
 173 }
 174
 175 /* vc_bypass_scale - VC bypass method of voltage scaling */
 176 int omap_vc_bypass_scale(struct voltagedomain *voltdm,
 177                          unsigned long target_volt)
 178 {
 179         struct omap_vc_channel *vc = voltdm->vc;
 180         u32 loop_cnt = 0, retries_cnt = 0;
 181         u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
 182         u8 target_vsel, current_vsel;
 183         int ret;
 184
 185         ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
 186         if (ret)
 187                 return ret;
 188
 189         vc_valid = vc->common->valid;
 190         vc_bypass_val_reg = vc->common->bypass_val_reg;
 191         vc_bypass_value = (target_vsel << vc->common->data_shift) |
 192                 (vc->volt_reg_addr << vc->common->regaddr_shift) |
 193                 (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
 194
 195         voltdm->write(vc_bypass_value, vc_bypass_val_reg);
 196         voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
 197
 198         vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 199         /*
 200          * Loop till the bypass command is acknowledged from the SMPS.
 201          * NOTE: This is legacy code. The loop count and retry count needs
 202          * to be revisited.
 203          */
 204         while (!(vc_bypass_value & vc_valid)) {
 205                 loop_cnt++;
 206
 207                 if (retries_cnt > 10) {
 208                         pr_warning("%s: Retry count exceeded\n", __func__);
 209                         return -ETIMEDOUT;
 210                 }
 211
 212                 if (loop_cnt > 50) {
 213                         retries_cnt++;
 214                         loop_cnt = 0;
 215                         udelay(10);
 216                 }
 217                 vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 218         }
 219
 220         omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
 221         return 0;
 222 }
 223
 224 static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
 225 {
 226         /*
 227          * Voltage Manager FSM parameters init
 228          * XXX This data should be passed in from the board file
 229          */
 230         voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
 231         voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
 232         voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
 233 }
 234
 235 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
 236 {
 237         static bool is_initialized;
 238
 239         if (is_initialized)
 240                 return;
 241
 242         omap3_vfsm_init(voltdm);
 243
 244         is_initialized = true;
 245 }
 246
 247
 248 /* OMAP4 specific voltage init functions */
 249 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
 250 {
 251         static bool is_initialized;
 252         u32 vc_val;
 253
 254         if (is_initialized)
 255                 return;
 256
 257         /* XXX These are magic numbers and do not belong! */
 258         vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
 259         voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
 260
 261         is_initialized = true;
 262 }
 263
 264 /**
 265  * omap_vc_i2c_init - initialize I2C interface to PMIC
 266  * @voltdm: voltage domain containing VC data
 267  *
 268  * Use PMIC supplied seetings for I2C high-speed mode and
 269  * master code (if set) and program the VC I2C configuration
 270  * register.
 271  *
 272  * The VC I2C configuration is common to all VC channels,
 273  * so this function only configures I2C for the first VC
 274  * channel registers.  All other VC channels will use the
 275  * same configuration.
 276  */
 277 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
 278 {
 279         struct omap_vc_channel *vc = voltdm->vc;
 280         static bool initialized;
 281         static bool i2c_high_speed;
 282         u8 mcode;
 283
 284         if (initialized) {
 285                 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
 286                         pr_warn("%s: I2C config for all channels must match.",
 287                                 __func__);
 288                 return;
 289         }
 290
 291         i2c_high_speed = voltdm->pmic->i2c_high_speed;
 292         if (i2c_high_speed)
 293                 voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
 294                             vc->common->i2c_cfg_hsen_mask,
 295                             vc->common->i2c_cfg_reg);
 296
 297         mcode = voltdm->pmic->i2c_mcode;
 298         if (mcode)
 299                 voltdm->rmw(vc->common->i2c_mcode_mask,
 300                             mcode << __ffs(vc->common->i2c_mcode_mask),
 301                             vc->common->i2c_cfg_reg);
 302
 303         initialized = true;
 304 }
 305
 306 void __init omap_vc_init_channel(struct voltagedomain *voltdm)
 307 {
 308         struct omap_vc_channel *vc = voltdm->vc;
 309         u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
 310         u32 val;
 311
 312         if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
 313                 pr_err("%s: PMIC info requried to configure vc for"
 314                         "vdd_%s not populated.Hence cannot initialize vc\n",
 315                         __func__, voltdm->name);
 316                 return;
 317         }
 318
 319         if (!voltdm->read || !voltdm->write) {
 320                 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 321                         __func__, voltdm->name);
 322                 return;
 323         }
 324
 325         vc->cfg_channel = 0;
 326         if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
 327                 vc_cfg_bits = &vc_mutant_channel_cfg;
 328         else
 329                 vc_cfg_bits = &vc_default_channel_cfg;
 330
 331         /* get PMIC/board specific settings */
 332         vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
 333         vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
 334         vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
 335         vc->setup_time = voltdm->pmic->volt_setup_time;
 336
 337         /* Configure the i2c slave address for this VC */
 338         voltdm->rmw(vc->smps_sa_mask,
 339                     vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
 340                     vc->common->smps_sa_reg);
 341         vc->cfg_channel |= vc_cfg_bits->sa;
 342
 343         /*
 344          * Configure the PMIC register addresses.
 345          */
 346         voltdm->rmw(vc->smps_volra_mask,
 347                     vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
 348                     vc->common->smps_volra_reg);
 349         vc->cfg_channel |= vc_cfg_bits->rav;
 350
 351         if (vc->cmd_reg_addr) {
 352                 voltdm->rmw(vc->smps_cmdra_mask,
 353                             vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
 354                             vc->common->smps_cmdra_reg);
 355                 vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
 356         }
 357
 358         /* Set up the on, inactive, retention and off voltage */
 359         on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
 360         onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
 361         ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
 362         off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
 363         val = ((on_vsel << vc->common->cmd_on_shift) |
 364                (onlp_vsel << vc->common->cmd_onlp_shift) |
 365                (ret_vsel << vc->common->cmd_ret_shift) |
 366                (off_vsel << vc->common->cmd_off_shift));
 367         voltdm->write(val, vc->cmdval_reg);
 368         vc->cfg_channel |= vc_cfg_bits->cmd;
 369
 370         /* Channel configuration */
 371         omap_vc_config_channel(voltdm);
 372
 373         /* Configure the setup times */
 374         voltdm->rmw(voltdm->vfsm->voltsetup_mask,
 375                     vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
 376                     voltdm->vfsm->voltsetup_reg);
 377
 378         omap_vc_i2c_init(voltdm);
 379
 380         if (cpu_is_omap34xx())
 381                 omap3_vc_init_channel(voltdm);
 382         else if (cpu_is_omap44xx())
 383                 omap4_vc_init_channel(voltdm);
 384 }
 385