arch/arm/mach-omap2/vc.c

   1 /*
   2  * OMAP Voltage Controller (VC) interface
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/bug.h>
  14
  15 #include "soc.h"
  16 #include "voltage.h"
  17 #include "vc.h"
  18 #include "prm-regbits-34xx.h"
  19 #include "prm-regbits-44xx.h"
  20 #include "prm44xx.h"
  21
  22 /**
  23  * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
  24  * @sa: bit for slave address
  25  * @rav: bit for voltage configuration register
  26  * @rac: bit for command configuration register
  27  * @racen: enable bit for RAC
  28  * @cmd: bit for command value set selection
  29  *
  30  * Channel configuration bits, common for OMAP3+
  31  * OMAP3 register: PRM_VC_CH_CONF
  32  * OMAP4 register: PRM_VC_CFG_CHANNEL
  33  * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
  34  */
  35 struct omap_vc_channel_cfg {
  36         u8 sa;
  37         u8 rav;
  38         u8 rac;
  39         u8 racen;
  40         u8 cmd;
  41 };
  42
  43 static struct omap_vc_channel_cfg vc_default_channel_cfg = {
  44         .sa    = BIT(0),
  45         .rav   = BIT(1),
  46         .rac   = BIT(2),
  47         .racen = BIT(3),
  48         .cmd   = BIT(4),
  49 };
  50
  51 /*
  52  * On OMAP3+, all VC channels have the above default bitfield
  53  * configuration, except the OMAP4 MPU channel.  This appears
  54  * to be a freak accident as every other VC channel has the
  55  * default configuration, thus creating a mutant channel config.
  56  */
  57 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
  58         .sa    = BIT(0),
  59         .rav   = BIT(2),
  60         .rac   = BIT(3),
  61         .racen = BIT(4),
  62         .cmd   = BIT(1),
  63 };
  64
  65 static struct omap_vc_channel_cfg *vc_cfg_bits;
  66 #define CFG_CHANNEL_MASK 0x1f
  67
  68 /**
  69  * omap_vc_config_channel - configure VC channel to PMIC mappings
  70  * @voltdm: pointer to voltagdomain defining the desired VC channel
  71  *
  72  * Configures the VC channel to PMIC mappings for the following
  73  * PMIC settings
  74  * - i2c slave address (SA)
  75  * - voltage configuration address (RAV)
  76  * - command configuration address (RAC) and enable bit (RACEN)
  77  * - command values for ON, ONLP, RET and OFF (CMD)
  78  *
  79  * This function currently only allows flexible configuration of the
  80  * non-default channel.  Starting with OMAP4, there are more than 2
  81  * channels, with one defined as the default (on OMAP4, it's MPU.)
  82  * Only the non-default channel can be configured.
  83  */
  84 static int omap_vc_config_channel(struct voltagedomain *voltdm)
  85 {
  86         struct omap_vc_channel *vc = voltdm->vc;
  87
  88         /*
  89          * For default channel, the only configurable bit is RACEN.
  90          * All others must stay at zero (see function comment above.)
  91          */
  92         if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
  93                 vc->cfg_channel &= vc_cfg_bits->racen;
  94
  95         voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
  96                     vc->cfg_channel << vc->cfg_channel_sa_shift,
  97                     vc->cfg_channel_reg);
  98
  99         return 0;
 100 }
 101
 102 /* Voltage scale and accessory APIs */
 103 int omap_vc_pre_scale(struct voltagedomain *voltdm,
 104                       unsigned long target_volt,
 105                       u8 *target_vsel, u8 *current_vsel)
 106 {
 107         struct omap_vc_channel *vc = voltdm->vc;
 108         u32 vc_cmdval;
 109
 110         /* Check if sufficient pmic info is available for this vdd */
 111         if (!voltdm->pmic) {
 112                 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
 113                         __func__, voltdm->name);
 114                 return -EINVAL;
 115         }
 116
 117         if (!voltdm->pmic->uv_to_vsel) {
 118                 pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
 119                        __func__, voltdm->name);
 120                 return -ENODATA;
 121         }
 122
 123         if (!voltdm->read || !voltdm->write) {
 124                 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 125                         __func__, voltdm->name);
 126                 return -EINVAL;
 127         }
 128
 129         *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
 130         *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
 131
 132         /* Setting the ON voltage to the new target voltage */
 133         vc_cmdval = voltdm->read(vc->cmdval_reg);
 134         vc_cmdval &= ~vc->common->cmd_on_mask;
 135         vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
 136         voltdm->write(vc_cmdval, vc->cmdval_reg);
 137
 138         omap_vp_update_errorgain(voltdm, target_volt);
 139
 140         return 0;
 141 }
 142
 143 void omap_vc_post_scale(struct voltagedomain *voltdm,
 144                         unsigned long target_volt,
 145                         u8 target_vsel, u8 current_vsel)
 146 {
 147         u32 smps_steps = 0, smps_delay = 0;
 148
 149         smps_steps = abs(target_vsel - current_vsel);
 150         /* SMPS slew rate / step size. 2us added as buffer. */
 151         smps_delay = ((smps_steps * voltdm->pmic->step_size) /
 152                         voltdm->pmic->slew_rate) + 2;
 153         udelay(smps_delay);
 154 }
 155
 156 /* vc_bypass_scale - VC bypass method of voltage scaling */
 157 int omap_vc_bypass_scale(struct voltagedomain *voltdm,
 158                          unsigned long target_volt)
 159 {
 160         struct omap_vc_channel *vc = voltdm->vc;
 161         u32 loop_cnt = 0, retries_cnt = 0;
 162         u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
 163         u8 target_vsel, current_vsel;
 164         int ret;
 165
 166         ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
 167         if (ret)
 168                 return ret;
 169
 170         vc_valid = vc->common->valid;
 171         vc_bypass_val_reg = vc->common->bypass_val_reg;
 172         vc_bypass_value = (target_vsel << vc->common->data_shift) |
 173                 (vc->volt_reg_addr << vc->common->regaddr_shift) |
 174                 (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
 175
 176         voltdm->write(vc_bypass_value, vc_bypass_val_reg);
 177         voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
 178
 179         vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 180         /*
 181          * Loop till the bypass command is acknowledged from the SMPS.
 182          * NOTE: This is legacy code. The loop count and retry count needs
 183          * to be revisited.
 184          */
 185         while (!(vc_bypass_value & vc_valid)) {
 186                 loop_cnt++;
 187
 188                 if (retries_cnt > 10) {
 189                         pr_warning("%s: Retry count exceeded\n", __func__);
 190                         return -ETIMEDOUT;
 191                 }
 192
 193                 if (loop_cnt > 50) {
 194                         retries_cnt++;
 195                         loop_cnt = 0;
 196                         udelay(10);
 197                 }
 198                 vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 199         }
 200
 201         omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
 202         return 0;
 203 }
 204
 205 static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
 206 {
 207         /*
 208          * Voltage Manager FSM parameters init
 209          * XXX This data should be passed in from the board file
 210          */
 211         voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
 212         voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
 213         voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
 214 }
 215
 216 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
 217 {
 218         static bool is_initialized;
 219
 220         if (is_initialized)
 221                 return;
 222
 223         omap3_vfsm_init(voltdm);
 224
 225         is_initialized = true;
 226 }
 227
 228
 229 /* OMAP4 specific voltage init functions */
 230 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
 231 {
 232         static bool is_initialized;
 233         u32 vc_val;
 234
 235         if (is_initialized)
 236                 return;
 237
 238         /* XXX These are magic numbers and do not belong! */
 239         vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
 240         voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
 241
 242         is_initialized = true;
 243 }
 244
 245 /**
 246  * omap_vc_i2c_init - initialize I2C interface to PMIC
 247  * @voltdm: voltage domain containing VC data
 248  *
 249  * Use PMIC supplied settings for I2C high-speed mode and
 250  * master code (if set) and program the VC I2C configuration
 251  * register.
 252  *
 253  * The VC I2C configuration is common to all VC channels,
 254  * so this function only configures I2C for the first VC
 255  * channel registers.  All other VC channels will use the
 256  * same configuration.
 257  */
 258 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
 259 {
 260         struct omap_vc_channel *vc = voltdm->vc;
 261         static bool initialized;
 262         static bool i2c_high_speed;
 263         u8 mcode;
 264
 265         if (initialized) {
 266                 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
 267                         pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
 268                                 __func__, voltdm->name, i2c_high_speed);
 269                 return;
 270         }
 271
 272         i2c_high_speed = voltdm->pmic->i2c_high_speed;
 273         if (i2c_high_speed)
 274                 voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
 275                             vc->common->i2c_cfg_hsen_mask,
 276                             vc->common->i2c_cfg_reg);
 277
 278         mcode = voltdm->pmic->i2c_mcode;
 279         if (mcode)
 280                 voltdm->rmw(vc->common->i2c_mcode_mask,
 281                             mcode << __ffs(vc->common->i2c_mcode_mask),
 282                             vc->common->i2c_cfg_reg);
 283
 284         initialized = true;
 285 }
 286
 287 void __init omap_vc_init_channel(struct voltagedomain *voltdm)
 288 {
 289         struct omap_vc_channel *vc = voltdm->vc;
 290         u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
 291         u32 val;
 292
 293         if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
 294                 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
 295                 return;
 296         }
 297
 298         if (!voltdm->read || !voltdm->write) {
 299                 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 300                         __func__, voltdm->name);
 301                 return;
 302         }
 303
 304         vc->cfg_channel = 0;
 305         if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
 306                 vc_cfg_bits = &vc_mutant_channel_cfg;
 307         else
 308                 vc_cfg_bits = &vc_default_channel_cfg;
 309
 310         /* get PMIC/board specific settings */
 311         vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
 312         vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
 313         vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
 314         vc->setup_time = voltdm->pmic->volt_setup_time;
 315
 316         /* Configure the i2c slave address for this VC */
 317         voltdm->rmw(vc->smps_sa_mask,
 318                     vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
 319                     vc->smps_sa_reg);
 320         vc->cfg_channel |= vc_cfg_bits->sa;
 321
 322         /*
 323          * Configure the PMIC register addresses.
 324          */
 325         voltdm->rmw(vc->smps_volra_mask,
 326                     vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
 327                     vc->smps_volra_reg);
 328         vc->cfg_channel |= vc_cfg_bits->rav;
 329
 330         if (vc->cmd_reg_addr) {
 331                 voltdm->rmw(vc->smps_cmdra_mask,
 332                             vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
 333                             vc->smps_cmdra_reg);
 334                 vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
 335         }
 336
 337         /* Set up the on, inactive, retention and off voltage */
 338         on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
 339         onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
 340         ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
 341         off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
 342         val = ((on_vsel << vc->common->cmd_on_shift) |
 343                (onlp_vsel << vc->common->cmd_onlp_shift) |
 344                (ret_vsel << vc->common->cmd_ret_shift) |
 345                (off_vsel << vc->common->cmd_off_shift));
 346         voltdm->write(val, vc->cmdval_reg);
 347         vc->cfg_channel |= vc_cfg_bits->cmd;
 348
 349         /* Channel configuration */
 350         omap_vc_config_channel(voltdm);
 351
 352         /* Configure the setup times */
 353         voltdm->rmw(voltdm->vfsm->voltsetup_mask,
 354                     vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
 355                     voltdm->vfsm->voltsetup_reg);
 356
 357         omap_vc_i2c_init(voltdm);
 358
 359         if (cpu_is_omap34xx())
 360                 omap3_vc_init_channel(voltdm);
 361         else if (cpu_is_omap44xx())
 362                 omap4_vc_init_channel(voltdm);
 363 }
 364