2 * arch/arm/mach-pnx4008/clock.c
4 * Clock control driver for PNX4008
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 * Generic clock management functions are partially based on:
8 * linux/arch/arm/mach-omap/clock.c
10 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
25 #include <asm/clkdev.h>
27 #include <mach/hardware.h>
28 #include <mach/clock.h>
31 /*forward declaration*/
32 static struct clk per_ck;
33 static struct clk hclk_ck;
34 static struct clk ck_1MHz;
35 static struct clk ck_13MHz;
36 static struct clk ck_pll1;
37 static int local_set_rate(struct clk *clk, u32 rate);
39 static inline void clock_lock(void)
44 static inline void clock_unlock(void)
49 static void propagate_rate(struct clk *clk)
54 while (tmp_clk->propagate_next) {
55 tmp_clk = tmp_clk->propagate_next;
56 local_set_rate(tmp_clk, tmp_clk->user_rate);
60 static void clk_reg_disable(struct clk *clk)
63 __raw_writel(__raw_readl(clk->enable_reg) &
64 ~(1 << clk->enable_shift), clk->enable_reg);
67 static int clk_reg_enable(struct clk *clk)
70 __raw_writel(__raw_readl(clk->enable_reg) |
71 (1 << clk->enable_shift), clk->enable_reg);
75 static inline void clk_reg_disable1(struct clk *clk)
78 __raw_writel(__raw_readl(clk->enable_reg1) &
79 ~(1 << clk->enable_shift1), clk->enable_reg1);
82 static inline void clk_reg_enable1(struct clk *clk)
85 __raw_writel(__raw_readl(clk->enable_reg1) |
86 (1 << clk->enable_shift1), clk->enable_reg1);
89 static int clk_wait_for_pll_lock(struct clk *clk)
93 while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ; /*wait for PLL to lock */
95 if (!(__raw_readl(clk->scale_reg) & 1)) {
97 "%s ERROR: failed to lock, scale reg data: %x\n",
98 clk->name, __raw_readl(clk->scale_reg));
104 static int switch_to_dirty_13mhz(struct clk *clk)
113 clk_reg_enable1(clk);
115 tmp_reg = __raw_readl(clk->parent_switch_reg);
116 /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
117 if (!(tmp_reg & 1)) {
118 tmp_reg |= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */
119 __raw_writel(tmp_reg, clk->parent_switch_reg);
121 while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13'MHz selection status */
123 if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
125 "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
126 clk->name, __raw_readl(clk->parent_switch_reg));
132 clk_reg_disable1(clk);
137 static int switch_to_clean_13mhz(struct clk *clk)
146 clk_reg_enable1(clk);
148 tmp_reg = __raw_readl(clk->parent_switch_reg);
149 /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
151 tmp_reg &= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */
152 __raw_writel(tmp_reg, clk->parent_switch_reg);
154 while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13MHz selection status */
156 if (__raw_readl(clk->parent_switch_reg) & 1) {
158 "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
159 clk->name, __raw_readl(clk->parent_switch_reg));
165 clk_reg_disable1(clk);
170 static int set_13MHz_parent(struct clk *clk, struct clk *parent)
174 if (parent == &ck_13MHz)
175 ret = switch_to_clean_13mhz(clk);
176 else if (parent == &ck_pll1)
177 ret = switch_to_dirty_13mhz(clk);
182 #define PLL160_MIN_FCCO 156000
183 #define PLL160_MAX_FCCO 320000
186 * Calculate pll160 settings.
187 * Possible input: up to 320MHz with step of clk->parent->rate.
188 * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
189 * Ignored paths: "feedback" (bit 13 set), "div-by-N".
190 * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
191 * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
192 * Please refer to PNX4008 IC manual for details.
195 static int pll160_set_rate(struct clk *clk, u32 rate)
197 u32 tmp_reg, tmp_m, tmp_2p, i;
201 parent_rate = clk->parent->rate;
206 /* set direct run for ARM or disable output for others */
207 clk_reg_disable(clk);
209 /* disable source input as well (ignored for ARM) */
210 clk_reg_disable1(clk);
212 tmp_reg = __raw_readl(clk->scale_reg);
213 tmp_reg &= ~0x1ffff; /*clear all settings, power down */
214 __raw_writel(tmp_reg, clk->scale_reg);
216 rate -= rate % parent_rate; /*round down the input */
218 if (rate > PLL160_MAX_FCCO)
219 rate = PLL160_MAX_FCCO;
227 clk_reg_enable1(clk);
228 tmp_reg = __raw_readl(clk->scale_reg);
230 if (rate == parent_rate) {
231 /*enter direct bypass mode */
232 tmp_reg |= ((1 << 14) | (1 << 15));
233 __raw_writel(tmp_reg, clk->scale_reg);
234 clk->rate = parent_rate;
241 for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
242 if (rate * tmp_2p >= PLL160_MIN_FCCO)
248 tmp_reg |= ((i - 1) << 11);
250 tmp_reg |= (1 << 14); /*direct mode, no divide */
252 tmp_m = rate * tmp_2p;
253 tmp_m /= parent_rate;
255 tmp_reg |= (tmp_m - 1) << 1; /*calculate M */
256 tmp_reg |= (1 << 16); /*power up PLL */
257 __raw_writel(tmp_reg, clk->scale_reg);
259 if (clk_wait_for_pll_lock(clk) < 0) {
260 clk_reg_disable(clk);
261 clk_reg_disable1(clk);
263 tmp_reg = __raw_readl(clk->scale_reg);
264 tmp_reg &= ~0x1ffff; /*clear all settings, power down */
265 __raw_writel(tmp_reg, clk->scale_reg);
271 clk->rate = (tmp_m * parent_rate) / tmp_2p;
273 if (clk->flags & RATE_PROPAGATES)
283 /*configure PER_CLK*/
284 static int per_clk_set_rate(struct clk *clk, u32 rate)
288 tmp = __raw_readl(clk->scale_reg);
290 tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
291 __raw_writel(tmp, clk->scale_reg);
297 static int hclk_set_rate(struct clk *clk, u32 rate)
300 tmp = __raw_readl(clk->scale_reg);
313 __raw_writel(tmp, clk->scale_reg);
318 static u32 hclk_round_rate(struct clk *clk, u32 rate)
328 static u32 per_clk_round_rate(struct clk *clk, u32 rate)
330 return CLK_RATE_13MHZ;
333 static int on_off_set_rate(struct clk *clk, u32 rate)
339 clk_reg_disable(clk);
345 static int on_off_inv_set_rate(struct clk *clk, u32 rate)
348 clk_reg_disable(clk); /*enable bit is inverted */
357 static u32 on_off_round_rate(struct clk *clk, u32 rate)
359 return (rate ? 1 : 0);
362 static u32 pll4_round_rate(struct clk *clk, u32 rate)
364 if (rate > CLK_RATE_208MHZ)
365 rate = CLK_RATE_208MHZ;
366 if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
367 rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
368 return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
371 static u32 pll3_round_rate(struct clk *clk, u32 rate)
373 if (rate > CLK_RATE_208MHZ)
374 rate = CLK_RATE_208MHZ;
375 return (rate - rate % CLK_RATE_13MHZ);
378 static u32 pll5_round_rate(struct clk *clk, u32 rate)
380 return (rate ? CLK_RATE_48MHZ : 0);
383 static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
385 return (rate ? CLK_RATE_13MHZ : 0);
388 static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
391 clk_reg_disable(clk); /*enable bit is inverted */
393 clk->rate = CLK_RATE_13MHZ;
394 ck_1MHz.rate = CLK_RATE_1MHZ;
403 static int pll1_set_rate(struct clk *clk, u32 rate)
405 #if 0 /* doesn't work on some boards, probably a HW BUG */
407 clk_reg_disable(clk); /*enable bit is inverted */
408 if (!clk_wait_for_pll_lock(clk)) {
409 clk->rate = CLK_RATE_13MHZ;
425 static struct clk osc_13MHz = {
428 .rate = CLK_RATE_13MHZ,
431 static struct clk ck_13MHz = {
433 .parent = &osc_13MHz,
434 .flags = NEEDS_INITIALIZATION,
435 .round_rate = &ck_13MHz_round_rate,
436 .set_rate = &ck_13MHz_set_rate,
437 .enable_reg = OSC13CTRL_REG,
439 .rate = CLK_RATE_13MHZ,
442 static struct clk osc_32KHz = {
445 .rate = CLK_RATE_32KHZ,
449 static struct clk ck_1MHz = {
451 .flags = FIXED_RATE | PARENT_SET_RATE,
455 /* PLL1 (397) - provides 13' MHz clock */
456 static struct clk ck_pll1 = {
458 .parent = &osc_32KHz,
459 .flags = NEEDS_INITIALIZATION,
460 .round_rate = &ck_13MHz_round_rate,
461 .set_rate = &pll1_set_rate,
462 .enable_reg = PLLCTRL_REG,
464 .scale_reg = PLLCTRL_REG,
465 .rate = CLK_RATE_13MHZ,
469 static struct clk ck_pll4 = {
472 .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
473 .propagate_next = &per_ck,
474 .round_rate = &pll4_round_rate,
475 .set_rate = &pll160_set_rate,
476 .rate = CLK_RATE_208MHZ,
477 .scale_reg = HCLKPLLCTRL_REG,
478 .enable_reg = PWRCTRL_REG,
480 .parent_switch_reg = SYSCLKCTRL_REG,
481 .set_parent = &set_13MHz_parent,
485 static struct clk ck_pll5 = {
488 .flags = NEEDS_INITIALIZATION,
489 .round_rate = &pll5_round_rate,
490 .set_rate = &pll160_set_rate,
491 .scale_reg = USBCTRL_REG,
492 .enable_reg = USBCTRL_REG,
494 .enable_reg1 = USBCTRL_REG,
498 /* XPERTTeak DSP PLL */
499 static struct clk ck_pll3 = {
502 .flags = NEEDS_INITIALIZATION,
503 .round_rate = &pll3_round_rate,
504 .set_rate = &pll160_set_rate,
505 .scale_reg = DSPPLLCTRL_REG,
506 .enable_reg = DSPCLKCTRL_REG,
508 .enable_reg1 = DSPCLKCTRL_REG,
510 .parent_switch_reg = DSPCLKCTRL_REG,
511 .set_parent = &set_13MHz_parent,
514 static struct clk hclk_ck = {
517 .flags = PARENT_SET_RATE,
518 .set_rate = &hclk_set_rate,
519 .round_rate = &hclk_round_rate,
520 .scale_reg = HCLKDIVCTRL_REG,
525 static struct clk per_ck = {
529 .propagate_next = &hclk_ck,
530 .set_rate = &per_clk_set_rate,
531 .round_rate = &per_clk_round_rate,
532 .scale_reg = HCLKDIVCTRL_REG,
533 .rate = CLK_RATE_13MHZ,
534 .user_rate = CLK_RATE_13MHZ,
537 static struct clk m2hclk_ck = {
540 .flags = NEEDS_INITIALIZATION,
541 .round_rate = &on_off_round_rate,
542 .set_rate = &on_off_inv_set_rate,
545 .enable_reg = PWRCTRL_REG,
548 static struct clk vfp9_ck = {
551 .flags = NEEDS_INITIALIZATION,
552 .round_rate = &on_off_round_rate,
553 .set_rate = &on_off_set_rate,
556 .enable_reg = VFP9CLKCTRL_REG,
559 static struct clk keyscan_ck = {
560 .name = "keyscan_ck",
561 .parent = &osc_32KHz,
562 .flags = NEEDS_INITIALIZATION,
563 .round_rate = &on_off_round_rate,
564 .set_rate = &on_off_set_rate,
566 .enable_reg = KEYCLKCTRL_REG,
569 static struct clk touch_ck = {
571 .parent = &osc_32KHz,
572 .flags = NEEDS_INITIALIZATION,
573 .round_rate = &on_off_round_rate,
574 .set_rate = &on_off_set_rate,
576 .enable_reg = TSCLKCTRL_REG,
579 static struct clk pwm1_ck = {
581 .parent = &osc_32KHz,
582 .flags = NEEDS_INITIALIZATION,
583 .round_rate = &on_off_round_rate,
584 .set_rate = &on_off_set_rate,
586 .enable_reg = PWMCLKCTRL_REG,
589 static struct clk pwm2_ck = {
591 .parent = &osc_32KHz,
592 .flags = NEEDS_INITIALIZATION,
593 .round_rate = &on_off_round_rate,
594 .set_rate = &on_off_set_rate,
596 .enable_reg = PWMCLKCTRL_REG,
599 static struct clk jpeg_ck = {
602 .flags = NEEDS_INITIALIZATION,
603 .round_rate = &on_off_round_rate,
604 .set_rate = &on_off_set_rate,
606 .enable_reg = JPEGCLKCTRL_REG,
609 static struct clk ms_ck = {
612 .flags = NEEDS_INITIALIZATION,
613 .round_rate = &on_off_round_rate,
614 .set_rate = &on_off_set_rate,
616 .enable_reg = MSCTRL_REG,
619 static struct clk dum_ck = {
622 .flags = NEEDS_INITIALIZATION,
623 .round_rate = &on_off_round_rate,
624 .set_rate = &on_off_set_rate,
626 .enable_reg = DUMCLKCTRL_REG,
629 static struct clk flash_ck = {
632 .round_rate = &on_off_round_rate,
633 .set_rate = &on_off_set_rate,
634 .enable_shift = 1, /* Only MLC clock supported */
635 .enable_reg = FLASHCLKCTRL_REG,
638 static struct clk i2c0_ck = {
641 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
643 .enable_reg = I2CCLKCTRL_REG,
645 .enable = clk_reg_enable,
646 .disable = clk_reg_disable,
649 static struct clk i2c1_ck = {
652 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
654 .enable_reg = I2CCLKCTRL_REG,
656 .enable = clk_reg_enable,
657 .disable = clk_reg_disable,
660 static struct clk i2c2_ck = {
663 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
665 .enable_reg = USB_OTG_CLKCTRL_REG,
667 .enable = clk_reg_enable,
668 .disable = clk_reg_disable,
671 static struct clk spi0_ck = {
674 .flags = NEEDS_INITIALIZATION,
675 .round_rate = &on_off_round_rate,
676 .set_rate = &on_off_set_rate,
678 .enable_reg = SPICTRL_REG,
681 static struct clk spi1_ck = {
684 .flags = NEEDS_INITIALIZATION,
685 .round_rate = &on_off_round_rate,
686 .set_rate = &on_off_set_rate,
688 .enable_reg = SPICTRL_REG,
691 static struct clk dma_ck = {
694 .round_rate = &on_off_round_rate,
695 .set_rate = &on_off_set_rate,
697 .enable_reg = DMACLKCTRL_REG,
700 static struct clk uart3_ck = {
703 .flags = NEEDS_INITIALIZATION,
704 .round_rate = &on_off_round_rate,
705 .set_rate = &on_off_set_rate,
708 .enable_reg = UARTCLKCTRL_REG,
711 static struct clk uart4_ck = {
714 .flags = NEEDS_INITIALIZATION,
715 .round_rate = &on_off_round_rate,
716 .set_rate = &on_off_set_rate,
718 .enable_reg = UARTCLKCTRL_REG,
721 static struct clk uart5_ck = {
724 .flags = NEEDS_INITIALIZATION,
725 .round_rate = &on_off_round_rate,
726 .set_rate = &on_off_set_rate,
729 .enable_reg = UARTCLKCTRL_REG,
732 static struct clk uart6_ck = {
735 .flags = NEEDS_INITIALIZATION,
736 .round_rate = &on_off_round_rate,
737 .set_rate = &on_off_set_rate,
739 .enable_reg = UARTCLKCTRL_REG,
742 static struct clk wdt_ck = {
745 .flags = NEEDS_INITIALIZATION,
747 .enable_reg = TIMCLKCTRL_REG,
748 .enable = clk_reg_enable,
749 .disable = clk_reg_disable,
752 /* These clocks are visible outside this module
753 * and can be initialized
755 static struct clk *onchip_clks[] __initdata = {
785 static struct clk_lookup onchip_clkreg[] = {
786 { .clk = &ck_13MHz, .con_id = "ck_13MHz" },
787 { .clk = &ck_pll1, .con_id = "ck_pll1" },
788 { .clk = &ck_pll4, .con_id = "ck_pll4" },
789 { .clk = &ck_pll5, .con_id = "ck_pll5" },
790 { .clk = &ck_pll3, .con_id = "ck_pll3" },
791 { .clk = &vfp9_ck, .con_id = "vfp9_ck" },
792 { .clk = &m2hclk_ck, .con_id = "m2hclk_ck" },
793 { .clk = &hclk_ck, .con_id = "hclk_ck" },
794 { .clk = &dma_ck, .con_id = "dma_ck" },
795 { .clk = &flash_ck, .con_id = "flash_ck" },
796 { .clk = &dum_ck, .con_id = "dum_ck" },
797 { .clk = &keyscan_ck, .con_id = "keyscan_ck" },
798 { .clk = &pwm1_ck, .con_id = "pwm1_ck" },
799 { .clk = &pwm2_ck, .con_id = "pwm2_ck" },
800 { .clk = &jpeg_ck, .con_id = "jpeg_ck" },
801 { .clk = &ms_ck, .con_id = "ms_ck" },
802 { .clk = &touch_ck, .con_id = "touch_ck" },
803 { .clk = &i2c0_ck, .dev_id = "pnx-i2c.0" },
804 { .clk = &i2c1_ck, .dev_id = "pnx-i2c.1" },
805 { .clk = &i2c2_ck, .dev_id = "pnx-i2c.2" },
806 { .clk = &spi0_ck, .con_id = "spi0_ck" },
807 { .clk = &spi1_ck, .con_id = "spi1_ck" },
808 { .clk = &uart3_ck, .con_id = "uart3_ck" },
809 { .clk = &uart4_ck, .con_id = "uart4_ck" },
810 { .clk = &uart5_ck, .con_id = "uart5_ck" },
811 { .clk = &uart6_ck, .con_id = "uart6_ck" },
812 { .clk = &wdt_ck, .dev_id = "pnx4008-watchdog" },
815 static void local_clk_disable(struct clk *clk)
817 if (WARN_ON(clk->usecount == 0))
820 if (!(--clk->usecount)) {
823 else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
824 clk->set_rate(clk, 0);
826 local_clk_disable(clk->parent);
830 static int local_clk_enable(struct clk *clk)
834 if (clk->usecount == 0) {
836 ret = local_clk_enable(clk->parent);
842 ret = clk->enable(clk);
843 else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
845 ret = clk->set_rate(clk, clk->user_rate);
847 if (ret != 0 && clk->parent) {
848 local_clk_disable(clk->parent);
858 static int local_set_rate(struct clk *clk, u32 rate)
863 if (clk->user_rate == clk->rate && clk->parent->rate) {
864 /* if clock enabled or rate not set */
865 clk->user_rate = clk->round_rate(clk, rate);
866 ret = clk->set_rate(clk, clk->user_rate);
868 clk->user_rate = clk->round_rate(clk, rate);
874 int clk_set_rate(struct clk *clk, unsigned long rate)
878 if (clk->flags & FIXED_RATE)
882 if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
884 clk->user_rate = clk->round_rate(clk, rate);
885 /* parent clock needs to be refreshed
886 for the setting to take effect */
888 ret = local_set_rate(clk, rate);
897 EXPORT_SYMBOL(clk_set_rate);
899 unsigned long clk_get_rate(struct clk *clk)
907 EXPORT_SYMBOL(clk_get_rate);
909 int clk_enable(struct clk *clk)
914 ret = local_clk_enable(clk);
919 EXPORT_SYMBOL(clk_enable);
921 void clk_disable(struct clk *clk)
924 local_clk_disable(clk);
928 EXPORT_SYMBOL(clk_disable);
930 long clk_round_rate(struct clk *clk, unsigned long rate)
935 ret = clk->round_rate(clk, rate);
942 EXPORT_SYMBOL(clk_round_rate);
944 int clk_set_parent(struct clk *clk, struct clk *parent)
947 if (!clk->set_parent)
951 ret = clk->set_parent(clk, parent);
953 clk->parent = parent;
960 EXPORT_SYMBOL(clk_set_parent);
962 static int __init clk_init(void)
966 /* Disable autoclocking, as it doesn't seem to work */
967 __raw_writel(0xff, AUTOCLK_CTRL);
969 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
971 struct clk *clk = *clkp;
972 if (clk->flags & NEEDS_INITIALIZATION) {
974 clk->user_rate = clk->rate;
975 local_set_rate(clk, clk->user_rate);
977 clk->set_parent(clk, clk->parent);
979 if (clk->enable && clk->usecount)
981 if (clk->disable && !clk->usecount)
984 pr_debug("%s: clock %s, rate %ld\n",
985 __func__, clk->name, clk->rate);
988 local_clk_enable(&ck_pll4);
990 /* if ck_13MHz is not used, disable it. */
991 if (ck_13MHz.usecount == 0)
992 local_clk_disable(&ck_13MHz);
994 /* Disable autoclocking */
995 __raw_writeb(0xff, AUTOCLK_CTRL);
997 clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
1002 arch_initcall(clk_init);