2 * linux/arch/arm/mach-pxa/clock-pxa3xx.c
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
14 #include <mach/smemc.h>
15 #include <mach/pxa3xx-regs.h>
19 /* Crystal clock: 13MHz */
20 #define BASE_CLK 13000000
22 /* Ring Oscillator Clock: 60MHz */
23 #define RO_CLK 60000000
25 #define ACCR_D0CS (1 << 26)
26 #define ACCR_PCCE (1 << 11)
28 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
29 static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
32 * Get the clock frequency as reflected by CCSR and the turbo flag.
33 * We assume these values have been applied via a fcs.
34 * If info is not 0 we also display the current settings.
36 unsigned int pxa3xx_get_clk_frequency_khz(int info)
38 unsigned long acsr, xclkcfg;
39 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
41 /* Read XCLKCFG register turbo bit */
42 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
48 xn = (acsr >> 8) & 0x7;
49 hss = (acsr >> 14) & 0x3;
54 ro = acsr & ACCR_D0CS;
56 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
57 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
60 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
61 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
63 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
64 XL / 1000000, (XL % 1000000) / 10000, xl);
65 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
66 XN / 1000000, (XN % 1000000) / 10000, xn,
68 pr_info("HSIO bus clock: %d.%02dMHz\n",
69 HSS / 1000000, (HSS % 1000000) / 10000);
76 * Return the current AC97 clock frequency.
78 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
80 unsigned long rate = 312000000;
81 unsigned long ac97_div;
85 /* This may loose precision for some rates but won't for the
88 rate /= (ac97_div >> 12) & 0x7fff;
89 rate *= (ac97_div & 0xfff);
95 * Return the current HSIO bus clock frequency
97 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
100 unsigned int hss, hsio_clk;
104 hss = (acsr >> 14) & 0x3;
105 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
110 /* crystal frequency to static memory controller multiplier (SMCFS) */
111 static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
112 static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
114 static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
116 unsigned long acsr = ACSR;
117 unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
118 unsigned int smcfs = (acsr >> 23) & 0x7;
120 return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
121 df_clkdiv[(memclkcfg >> 16) & 0x3];
124 void clk_pxa3xx_cken_enable(struct clk *clk)
126 unsigned long mask = 1ul << (clk->cken & 0x1f);
134 void clk_pxa3xx_cken_disable(struct clk *clk)
136 unsigned long mask = 1ul << (clk->cken & 0x1f);
144 const struct clkops clk_pxa3xx_cken_ops = {
145 .enable = clk_pxa3xx_cken_enable,
146 .disable = clk_pxa3xx_cken_disable,
149 const struct clkops clk_pxa3xx_hsio_ops = {
150 .enable = clk_pxa3xx_cken_enable,
151 .disable = clk_pxa3xx_cken_disable,
152 .getrate = clk_pxa3xx_hsio_getrate,
155 const struct clkops clk_pxa3xx_ac97_ops = {
156 .enable = clk_pxa3xx_cken_enable,
157 .disable = clk_pxa3xx_cken_disable,
158 .getrate = clk_pxa3xx_ac97_getrate,
161 const struct clkops clk_pxa3xx_smemc_ops = {
162 .enable = clk_pxa3xx_cken_enable,
163 .disable = clk_pxa3xx_cken_disable,
164 .getrate = clk_pxa3xx_smemc_getrate,
167 static void clk_pout_enable(struct clk *clk)
172 static void clk_pout_disable(struct clk *clk)
177 const struct clkops clk_pxa3xx_pout_ops = {
178 .enable = clk_pout_enable,
179 .disable = clk_pout_disable,
183 static uint32_t cken[2];
184 static uint32_t accr;
186 static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state)
194 static int pxa3xx_clock_resume(struct sys_device *d)
202 #define pxa3xx_clock_suspend NULL
203 #define pxa3xx_clock_resume NULL
206 struct sysdev_class pxa3xx_clock_sysclass = {
207 .name = "pxa3xx-clock",
208 .suspend = pxa3xx_clock_suspend,
209 .resume = pxa3xx_clock_resume,
212 static int __init pxa3xx_clock_init(void)
214 if (cpu_is_pxa3xx() || cpu_is_pxa95x())
215 return sysdev_class_register(&pxa3xx_clock_sysclass);
218 postcore_initcall(pxa3xx_clock_init);