arch/arm/mach-pxa/generic.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/generic.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Jun 15, 2001
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code common to all PXA machines.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Since this file should be linked before any other machine specific file,
  15  * the __initcall() here will be executed first.  This serves as default
  16  * initialization stuff for PXA machines which can be overridden later if
  17  * need be.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/delay.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ioport.h>
  25 #include <linux/pm.h>
  26 #include <linux/string.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <asm/hardware.h>
  30 #include <asm/irq.h>
  31 #include <asm/system.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/mach/map.h>
  34
  35 #include <asm/arch/pxa-regs.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/udc.h>
  38 #include <asm/arch/pxafb.h>
  39 #include <asm/arch/mmc.h>
  40 #include <asm/arch/irda.h>
  41 #include <asm/arch/i2c.h>
  42
  43 #include "devices.h"
  44 #include "generic.h"
  45
  46 /*
  47  * Get the clock frequency as reflected by CCCR and the turbo flag.
  48  * We assume these values have been applied via a fcs.
  49  * If info is not 0 we also display the current settings.
  50  */
  51 unsigned int get_clk_frequency_khz(int info)
  52 {
  53         if (cpu_is_pxa21x() || cpu_is_pxa25x())
  54                 return pxa25x_get_clk_frequency_khz(info);
  55         else if (cpu_is_pxa27x())
  56                 return pxa27x_get_clk_frequency_khz(info);
  57         else
  58                 return pxa3xx_get_clk_frequency_khz(info);
  59 }
  60 EXPORT_SYMBOL(get_clk_frequency_khz);
  61
  62 /*
  63  * Return the current memory clock frequency in units of 10kHz
  64  */
  65 unsigned int get_memclk_frequency_10khz(void)
  66 {
  67         if (cpu_is_pxa21x() || cpu_is_pxa25x())
  68                 return pxa25x_get_memclk_frequency_10khz();
  69         else if (cpu_is_pxa27x())
  70                 return pxa27x_get_memclk_frequency_10khz();
  71         else
  72                 return pxa3xx_get_memclk_frequency_10khz();
  73 }
  74 EXPORT_SYMBOL(get_memclk_frequency_10khz);
  75
  76 /*
  77  * Handy function to set GPIO alternate functions
  78  */
  79 int pxa_last_gpio;
  80
  81 int pxa_gpio_mode(int gpio_mode)
  82 {
  83         unsigned long flags;
  84         int gpio = gpio_mode & GPIO_MD_MASK_NR;
  85         int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
  86         int gafr;
  87
  88         if (gpio > pxa_last_gpio)
  89                 return -EINVAL;
  90
  91         local_irq_save(flags);
  92         if (gpio_mode & GPIO_DFLT_LOW)
  93                 GPCR(gpio) = GPIO_bit(gpio);
  94         else if (gpio_mode & GPIO_DFLT_HIGH)
  95                 GPSR(gpio) = GPIO_bit(gpio);
  96         if (gpio_mode & GPIO_MD_MASK_DIR)
  97                 GPDR(gpio) |= GPIO_bit(gpio);
  98         else
  99                 GPDR(gpio) &= ~GPIO_bit(gpio);
 100         gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
 101         GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
 102         local_irq_restore(flags);
 103
 104         return 0;
 105 }
 106
 107 EXPORT_SYMBOL(pxa_gpio_mode);
 108
 109 int gpio_direction_input(unsigned gpio)
 110 {
 111         unsigned long flags;
 112         u32 mask;
 113
 114         if (gpio > pxa_last_gpio)
 115                 return -EINVAL;
 116
 117         mask = GPIO_bit(gpio);
 118         local_irq_save(flags);
 119         GPDR(gpio) &= ~mask;
 120         local_irq_restore(flags);
 121
 122         return 0;
 123 }
 124 EXPORT_SYMBOL(gpio_direction_input);
 125
 126 int gpio_direction_output(unsigned gpio, int value)
 127 {
 128         unsigned long flags;
 129         u32 mask;
 130
 131         if (gpio > pxa_last_gpio)
 132                 return -EINVAL;
 133
 134         mask = GPIO_bit(gpio);
 135         local_irq_save(flags);
 136         if (value)
 137                 GPSR(gpio) = mask;
 138         else
 139                 GPCR(gpio) = mask;
 140         GPDR(gpio) |= mask;
 141         local_irq_restore(flags);
 142
 143         return 0;
 144 }
 145 EXPORT_SYMBOL(gpio_direction_output);
 146
 147 /*
 148  * Return GPIO level
 149  */
 150 int pxa_gpio_get_value(unsigned gpio)
 151 {
 152         return __gpio_get_value(gpio);
 153 }
 154
 155 EXPORT_SYMBOL(pxa_gpio_get_value);
 156
 157 /*
 158  * Set output GPIO level
 159  */
 160 void pxa_gpio_set_value(unsigned gpio, int value)
 161 {
 162         __gpio_set_value(gpio, value);
 163 }
 164
 165 EXPORT_SYMBOL(pxa_gpio_set_value);
 166
 167 /*
 168  * Routine to safely enable or disable a clock in the CKEN
 169  */
 170 void __pxa_set_cken(int clock, int enable)
 171 {
 172         unsigned long flags;
 173         local_irq_save(flags);
 174
 175         if (enable)
 176                 CKEN |= (1 << clock);
 177         else
 178                 CKEN &= ~(1 << clock);
 179
 180         local_irq_restore(flags);
 181 }
 182
 183 EXPORT_SYMBOL(__pxa_set_cken);
 184
 185 /*
 186  * Intel PXA2xx internal register mapping.
 187  *
 188  * Note 1: not all PXA2xx variants implement all those addresses.
 189  *
 190  * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
 191  *         and cache flush area.
 192  */
 193 static struct map_desc standard_io_desc[] __initdata = {
 194         {       /* Devs */
 195                 .virtual        =  0xf2000000,
 196                 .pfn            = __phys_to_pfn(0x40000000),
 197                 .length         = 0x02000000,
 198                 .type           = MT_DEVICE
 199         }, {    /* LCD */
 200                 .virtual        =  0xf4000000,
 201                 .pfn            = __phys_to_pfn(0x44000000),
 202                 .length         = 0x00100000,
 203                 .type           = MT_DEVICE
 204         }, {    /* Mem Ctl */
 205                 .virtual        =  0xf6000000,
 206                 .pfn            = __phys_to_pfn(0x48000000),
 207                 .length         = 0x00100000,
 208                 .type           = MT_DEVICE
 209         }, {    /* USB host */
 210                 .virtual        =  0xf8000000,
 211                 .pfn            = __phys_to_pfn(0x4c000000),
 212                 .length         = 0x00100000,
 213                 .type           = MT_DEVICE
 214         }, {    /* Camera */
 215                 .virtual        =  0xfa000000,
 216                 .pfn            = __phys_to_pfn(0x50000000),
 217                 .length         = 0x00100000,
 218                 .type           = MT_DEVICE
 219         }, {    /* IMem ctl */
 220                 .virtual        =  0xfe000000,
 221                 .pfn            = __phys_to_pfn(0x58000000),
 222                 .length         = 0x00100000,
 223                 .type           = MT_DEVICE
 224         }, {    /* UNCACHED_PHYS_0 */
 225                 .virtual        = 0xff000000,
 226                 .pfn            = __phys_to_pfn(0x00000000),
 227                 .length         = 0x00100000,
 228                 .type           = MT_DEVICE
 229         }
 230 };
 231
 232 void __init pxa_map_io(void)
 233 {
 234         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
 235         get_clk_frequency_khz(1);
 236 }
 237
 238
 239 void __init pxa_register_device(struct platform_device *dev, void *data)
 240 {
 241         int ret;
 242
 243         dev->dev.platform_data = data;
 244
 245         ret = platform_device_register(dev);
 246         if (ret)
 247                 dev_err(&dev->dev, "unable to register device: %d\n", ret);
 248 }
 249
 250
 251 static struct resource pxamci_resources[] = {
 252         [0] = {
 253                 .start  = 0x41100000,
 254                 .end    = 0x41100fff,
 255                 .flags  = IORESOURCE_MEM,
 256         },
 257         [1] = {
 258                 .start  = IRQ_MMC,
 259                 .end    = IRQ_MMC,
 260                 .flags  = IORESOURCE_IRQ,
 261         },
 262 };
 263
 264 static u64 pxamci_dmamask = 0xffffffffUL;
 265
 266 struct platform_device pxa_device_mci = {
 267         .name           = "pxa2xx-mci",
 268         .id             = -1,
 269         .dev            = {
 270                 .dma_mask = &pxamci_dmamask,
 271                 .coherent_dma_mask = 0xffffffff,
 272         },
 273         .num_resources  = ARRAY_SIZE(pxamci_resources),
 274         .resource       = pxamci_resources,
 275 };
 276
 277 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
 278 {
 279         pxa_register_device(&pxa_device_mci, info);
 280 }
 281
 282
 283 static struct pxa2xx_udc_mach_info pxa_udc_info;
 284
 285 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
 286 {
 287         memcpy(&pxa_udc_info, info, sizeof *info);
 288 }
 289
 290 static struct resource pxa2xx_udc_resources[] = {
 291         [0] = {
 292                 .start  = 0x40600000,
 293                 .end    = 0x4060ffff,
 294                 .flags  = IORESOURCE_MEM,
 295         },
 296         [1] = {
 297                 .start  = IRQ_USB,
 298                 .end    = IRQ_USB,
 299                 .flags  = IORESOURCE_IRQ,
 300         },
 301 };
 302
 303 static u64 udc_dma_mask = ~(u32)0;
 304
 305 struct platform_device pxa_device_udc = {
 306         .name           = "pxa2xx-udc",
 307         .id             = -1,
 308         .resource       = pxa2xx_udc_resources,
 309         .num_resources  = ARRAY_SIZE(pxa2xx_udc_resources),
 310         .dev            =  {
 311                 .platform_data  = &pxa_udc_info,
 312                 .dma_mask       = &udc_dma_mask,
 313         }
 314 };
 315
 316 static struct resource pxafb_resources[] = {
 317         [0] = {
 318                 .start  = 0x44000000,
 319                 .end    = 0x4400ffff,
 320                 .flags  = IORESOURCE_MEM,
 321         },
 322         [1] = {
 323                 .start  = IRQ_LCD,
 324                 .end    = IRQ_LCD,
 325                 .flags  = IORESOURCE_IRQ,
 326         },
 327 };
 328
 329 static u64 fb_dma_mask = ~(u64)0;
 330
 331 struct platform_device pxa_device_fb = {
 332         .name           = "pxa2xx-fb",
 333         .id             = -1,
 334         .dev            = {
 335                 .dma_mask       = &fb_dma_mask,
 336                 .coherent_dma_mask = 0xffffffff,
 337         },
 338         .num_resources  = ARRAY_SIZE(pxafb_resources),
 339         .resource       = pxafb_resources,
 340 };
 341
 342 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
 343 {
 344         pxa_register_device(&pxa_device_fb, info);
 345 }
 346
 347 void __init set_pxa_fb_parent(struct device *parent_dev)
 348 {
 349         pxa_device_fb.dev.parent = parent_dev;
 350 }
 351
 352 static struct resource pxa_resource_ffuart[] = {
 353         {
 354                 .start  = __PREG(FFUART),
 355                 .end    = __PREG(FFUART) + 35,
 356                 .flags  = IORESOURCE_MEM,
 357         }, {
 358                 .start  = IRQ_FFUART,
 359                 .end    = IRQ_FFUART,
 360                 .flags  = IORESOURCE_IRQ,
 361         }
 362 };
 363
 364 struct platform_device pxa_device_ffuart= {
 365         .name           = "pxa2xx-uart",
 366         .id             = 0,
 367         .resource       = pxa_resource_ffuart,
 368         .num_resources  = ARRAY_SIZE(pxa_resource_ffuart),
 369 };
 370
 371 static struct resource pxa_resource_btuart[] = {
 372         {
 373                 .start  = __PREG(BTUART),
 374                 .end    = __PREG(BTUART) + 35,
 375                 .flags  = IORESOURCE_MEM,
 376         }, {
 377                 .start  = IRQ_BTUART,
 378                 .end    = IRQ_BTUART,
 379                 .flags  = IORESOURCE_IRQ,
 380         }
 381 };
 382
 383 struct platform_device pxa_device_btuart = {
 384         .name           = "pxa2xx-uart",
 385         .id             = 1,
 386         .resource       = pxa_resource_btuart,
 387         .num_resources  = ARRAY_SIZE(pxa_resource_btuart),
 388 };
 389
 390 static struct resource pxa_resource_stuart[] = {
 391         {
 392                 .start  = __PREG(STUART),
 393                 .end    = __PREG(STUART) + 35,
 394                 .flags  = IORESOURCE_MEM,
 395         }, {
 396                 .start  = IRQ_STUART,
 397                 .end    = IRQ_STUART,
 398                 .flags  = IORESOURCE_IRQ,
 399         }
 400 };
 401
 402 struct platform_device pxa_device_stuart = {
 403         .name           = "pxa2xx-uart",
 404         .id             = 2,
 405         .resource       = pxa_resource_stuart,
 406         .num_resources  = ARRAY_SIZE(pxa_resource_stuart),
 407 };
 408
 409 static struct resource pxa_resource_hwuart[] = {
 410         {
 411                 .start  = __PREG(HWUART),
 412                 .end    = __PREG(HWUART) + 47,
 413                 .flags  = IORESOURCE_MEM,
 414         }, {
 415                 .start  = IRQ_HWUART,
 416                 .end    = IRQ_HWUART,
 417                 .flags  = IORESOURCE_IRQ,
 418         }
 419 };
 420
 421 struct platform_device pxa_device_hwuart = {
 422         .name           = "pxa2xx-uart",
 423         .id             = 3,
 424         .resource       = pxa_resource_hwuart,
 425         .num_resources  = ARRAY_SIZE(pxa_resource_hwuart),
 426 };
 427
 428 static struct resource pxai2c_resources[] = {
 429         {
 430                 .start  = 0x40301680,
 431                 .end    = 0x403016a3,
 432                 .flags  = IORESOURCE_MEM,
 433         }, {
 434                 .start  = IRQ_I2C,
 435                 .end    = IRQ_I2C,
 436                 .flags  = IORESOURCE_IRQ,
 437         },
 438 };
 439
 440 struct platform_device pxa_device_i2c = {
 441         .name           = "pxa2xx-i2c",
 442         .id             = 0,
 443         .resource       = pxai2c_resources,
 444         .num_resources  = ARRAY_SIZE(pxai2c_resources),
 445 };
 446
 447 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
 448 {
 449         pxa_register_device(&pxa_device_i2c, info);
 450 }
 451
 452 static struct resource pxai2s_resources[] = {
 453         {
 454                 .start  = 0x40400000,
 455                 .end    = 0x40400083,
 456                 .flags  = IORESOURCE_MEM,
 457         }, {
 458                 .start  = IRQ_I2S,
 459                 .end    = IRQ_I2S,
 460                 .flags  = IORESOURCE_IRQ,
 461         },
 462 };
 463
 464 struct platform_device pxa_device_i2s = {
 465         .name           = "pxa2xx-i2s",
 466         .id             = -1,
 467         .resource       = pxai2s_resources,
 468         .num_resources  = ARRAY_SIZE(pxai2s_resources),
 469 };
 470
 471 static u64 pxaficp_dmamask = ~(u32)0;
 472
 473 struct platform_device pxa_device_ficp = {
 474         .name           = "pxa2xx-ir",
 475         .id             = -1,
 476         .dev            = {
 477                 .dma_mask = &pxaficp_dmamask,
 478                 .coherent_dma_mask = 0xffffffff,
 479         },
 480 };
 481
 482 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
 483 {
 484         pxa_register_device(&pxa_device_ficp, info);
 485 }
 486
 487 struct platform_device pxa_device_rtc = {
 488         .name           = "sa1100-rtc",
 489         .id             = -1,
 490 };
 491
 492 #ifdef CONFIG_PXA25x
 493
 494 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
 495
 496 static struct resource pxa25x_resource_ssp[] = {
 497         [0] = {
 498                 .start  = 0x41000000,
 499                 .end    = 0x4100001f,
 500                 .flags  = IORESOURCE_MEM,
 501         },
 502         [1] = {
 503                 .start  = IRQ_SSP,
 504                 .end    = IRQ_SSP,
 505                 .flags  = IORESOURCE_IRQ,
 506         },
 507         [2] = {
 508                 /* DRCMR for RX */
 509                 .start  = 13,
 510                 .end    = 13,
 511                 .flags  = IORESOURCE_DMA,
 512         },
 513         [3] = {
 514                 /* DRCMR for TX */
 515                 .start  = 14,
 516                 .end    = 14,
 517                 .flags  = IORESOURCE_DMA,
 518         },
 519 };
 520
 521 struct platform_device pxa25x_device_ssp = {
 522         .name           = "pxa25x-ssp",
 523         .id             = 0,
 524         .dev            = {
 525                 .dma_mask = &pxa25x_ssp_dma_mask,
 526                 .coherent_dma_mask = DMA_BIT_MASK(32),
 527         },
 528         .resource       = pxa25x_resource_ssp,
 529         .num_resources  = ARRAY_SIZE(pxa25x_resource_ssp),
 530 };
 531
 532 static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
 533
 534 static struct resource pxa25x_resource_nssp[] = {
 535         [0] = {
 536                 .start  = 0x41400000,
 537                 .end    = 0x4140002f,
 538                 .flags  = IORESOURCE_MEM,
 539         },
 540         [1] = {
 541                 .start  = IRQ_NSSP,
 542                 .end    = IRQ_NSSP,
 543                 .flags  = IORESOURCE_IRQ,
 544         },
 545         [2] = {
 546                 /* DRCMR for RX */
 547                 .start  = 15,
 548                 .end    = 15,
 549                 .flags  = IORESOURCE_DMA,
 550         },
 551         [3] = {
 552                 /* DRCMR for TX */
 553                 .start  = 16,
 554                 .end    = 16,
 555                 .flags  = IORESOURCE_DMA,
 556         },
 557 };
 558
 559 struct platform_device pxa25x_device_nssp = {
 560         .name           = "pxa25x-nssp",
 561         .id             = 1,
 562         .dev            = {
 563                 .dma_mask = &pxa25x_nssp_dma_mask,
 564                 .coherent_dma_mask = DMA_BIT_MASK(32),
 565         },
 566         .resource       = pxa25x_resource_nssp,
 567         .num_resources  = ARRAY_SIZE(pxa25x_resource_nssp),
 568 };
 569
 570 static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
 571
 572 static struct resource pxa25x_resource_assp[] = {
 573         [0] = {
 574                 .start  = 0x41500000,
 575                 .end    = 0x4150002f,
 576                 .flags  = IORESOURCE_MEM,
 577         },
 578         [1] = {
 579                 .start  = IRQ_ASSP,
 580                 .end    = IRQ_ASSP,
 581                 .flags  = IORESOURCE_IRQ,
 582         },
 583         [2] = {
 584                 /* DRCMR for RX */
 585                 .start  = 23,
 586                 .end    = 23,
 587                 .flags  = IORESOURCE_DMA,
 588         },
 589         [3] = {
 590                 /* DRCMR for TX */
 591                 .start  = 24,
 592                 .end    = 24,
 593                 .flags  = IORESOURCE_DMA,
 594         },
 595 };
 596
 597 struct platform_device pxa25x_device_assp = {
 598         /* ASSP is basically equivalent to NSSP */
 599         .name           = "pxa25x-nssp",
 600         .id             = 2,
 601         .dev            = {
 602                 .dma_mask = &pxa25x_assp_dma_mask,
 603                 .coherent_dma_mask = DMA_BIT_MASK(32),
 604         },
 605         .resource       = pxa25x_resource_assp,
 606         .num_resources  = ARRAY_SIZE(pxa25x_resource_assp),
 607 };
 608 #endif /* CONFIG_PXA25x */
 609
 610 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 611
 612 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
 613
 614 static struct resource pxa27x_resource_ssp1[] = {
 615         [0] = {
 616                 .start  = 0x41000000,
 617                 .end    = 0x4100003f,
 618                 .flags  = IORESOURCE_MEM,
 619         },
 620         [1] = {
 621                 .start  = IRQ_SSP,
 622                 .end    = IRQ_SSP,
 623                 .flags  = IORESOURCE_IRQ,
 624         },
 625         [2] = {
 626                 /* DRCMR for RX */
 627                 .start  = 13,
 628                 .end    = 13,
 629                 .flags  = IORESOURCE_DMA,
 630         },
 631         [3] = {
 632                 /* DRCMR for TX */
 633                 .start  = 14,
 634                 .end    = 14,
 635                 .flags  = IORESOURCE_DMA,
 636         },
 637 };
 638
 639 struct platform_device pxa27x_device_ssp1 = {
 640         .name           = "pxa27x-ssp",
 641         .id             = 0,
 642         .dev            = {
 643                 .dma_mask = &pxa27x_ssp1_dma_mask,
 644                 .coherent_dma_mask = DMA_BIT_MASK(32),
 645         },
 646         .resource       = pxa27x_resource_ssp1,
 647         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp1),
 648 };
 649
 650 static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
 651
 652 static struct resource pxa27x_resource_ssp2[] = {
 653         [0] = {
 654                 .start  = 0x41700000,
 655                 .end    = 0x4170003f,
 656                 .flags  = IORESOURCE_MEM,
 657         },
 658         [1] = {
 659                 .start  = IRQ_SSP2,
 660                 .end    = IRQ_SSP2,
 661                 .flags  = IORESOURCE_IRQ,
 662         },
 663         [2] = {
 664                 /* DRCMR for RX */
 665                 .start  = 15,
 666                 .end    = 15,
 667                 .flags  = IORESOURCE_DMA,
 668         },
 669         [3] = {
 670                 /* DRCMR for TX */
 671                 .start  = 16,
 672                 .end    = 16,
 673                 .flags  = IORESOURCE_DMA,
 674         },
 675 };
 676
 677 struct platform_device pxa27x_device_ssp2 = {
 678         .name           = "pxa27x-ssp",
 679         .id             = 1,
 680         .dev            = {
 681                 .dma_mask = &pxa27x_ssp2_dma_mask,
 682                 .coherent_dma_mask = DMA_BIT_MASK(32),
 683         },
 684         .resource       = pxa27x_resource_ssp2,
 685         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp2),
 686 };
 687
 688 static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
 689
 690 static struct resource pxa27x_resource_ssp3[] = {
 691         [0] = {
 692                 .start  = 0x41900000,
 693                 .end    = 0x4190003f,
 694                 .flags  = IORESOURCE_MEM,
 695         },
 696         [1] = {
 697                 .start  = IRQ_SSP3,
 698                 .end    = IRQ_SSP3,
 699                 .flags  = IORESOURCE_IRQ,
 700         },
 701         [2] = {
 702                 /* DRCMR for RX */
 703                 .start  = 66,
 704                 .end    = 66,
 705                 .flags  = IORESOURCE_DMA,
 706         },
 707         [3] = {
 708                 /* DRCMR for TX */
 709                 .start  = 67,
 710                 .end    = 67,
 711                 .flags  = IORESOURCE_DMA,
 712         },
 713 };
 714
 715 struct platform_device pxa27x_device_ssp3 = {
 716         .name           = "pxa27x-ssp",
 717         .id             = 2,
 718         .dev            = {
 719                 .dma_mask = &pxa27x_ssp3_dma_mask,
 720                 .coherent_dma_mask = DMA_BIT_MASK(32),
 721         },
 722         .resource       = pxa27x_resource_ssp3,
 723         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp3),
 724 };
 725 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
 726
 727 #ifdef CONFIG_PXA3xx
 728 static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
 729
 730 static struct resource pxa3xx_resource_ssp4[] = {
 731         [0] = {
 732                 .start  = 0x41a00000,
 733                 .end    = 0x41a0003f,
 734                 .flags  = IORESOURCE_MEM,
 735         },
 736         [1] = {
 737                 .start  = IRQ_SSP4,
 738                 .end    = IRQ_SSP4,
 739                 .flags  = IORESOURCE_IRQ,
 740         },
 741         [2] = {
 742                 /* DRCMR for RX */
 743                 .start  = 2,
 744                 .end    = 2,
 745                 .flags  = IORESOURCE_DMA,
 746         },
 747         [3] = {
 748                 /* DRCMR for TX */
 749                 .start  = 3,
 750                 .end    = 3,
 751                 .flags  = IORESOURCE_DMA,
 752         },
 753 };
 754
 755 struct platform_device pxa3xx_device_ssp4 = {
 756         /* PXA3xx SSP is basically equivalent to PXA27x */
 757         .name           = "pxa27x-ssp",
 758         .id             = 3,
 759         .dev            = {
 760                 .dma_mask = &pxa3xx_ssp4_dma_mask,
 761                 .coherent_dma_mask = DMA_BIT_MASK(32),
 762         },
 763         .resource       = pxa3xx_resource_ssp4,
 764         .num_resources  = ARRAY_SIZE(pxa3xx_resource_ssp4),
 765 };
 766 #endif /* CONFIG_PXA3xx */