2 * linux/arch/arm/mach-pxa/pxa27x.c
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
8 * Code specific to PXA27x aka Bulverde.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/gpio.h>
15 #include <linux/gpio-pxa.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/suspend.h>
20 #include <linux/platform_device.h>
21 #include <linux/syscore_ops.h>
23 #include <linux/irq.h>
24 #include <linux/i2c/pxa-i2c.h>
25 #include <linux/gpio.h>
27 #include <asm/mach/map.h>
28 #include <mach/hardware.h>
30 #include <asm/suspend.h>
31 #include <mach/irqs.h>
32 #include <mach/pxa27x.h>
33 #include <mach/reset.h>
34 #include <mach/ohci.h>
37 #include <mach/smemc.h>
43 void pxa27x_clear_otgph(void)
45 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
48 EXPORT_SYMBOL(pxa27x_clear_otgph);
50 static unsigned long ac97_reset_config[] = {
57 void pxa27x_assert_ac97reset(int reset_gpio, int on)
59 if (reset_gpio == 113)
60 pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
61 &ac97_reset_config[1], 1);
64 pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
65 &ac97_reset_config[3], 1);
67 EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
69 /* Crystal clock: 13MHz */
70 #define BASE_CLK 13000000
73 * Get the clock frequency as reflected by CCSR and the turbo flag.
74 * We assume these values have been applied via a fcs.
75 * If info is not 0 we also display the current settings.
77 unsigned int pxa27x_get_clk_frequency_khz(int info)
79 unsigned long ccsr, clkcfg;
80 unsigned int l, L, m, M, n2, N, S;
84 cccr_a = CCCR & (1 << 25);
86 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
87 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
88 t = clkcfg & (1 << 0);
89 ht = clkcfg & (1 << 2);
90 b = clkcfg & (1 << 3);
94 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
98 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
102 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
103 L / 1000000, (L % 1000000) / 10000, l );
104 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
105 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
107 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
108 M / 1000000, (M % 1000000) / 10000, m );
109 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
110 S / 1000000, (S % 1000000) / 10000 );
113 return (t) ? (N/1000) : (L/1000);
117 * Return the current mem clock frequency as reflected by CCCR[A], B, and L
119 static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
121 unsigned long ccsr, clkcfg;
122 unsigned int l, L, m, M;
126 cccr_a = CCCR & (1 << 25);
128 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
129 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
130 b = clkcfg & (1 << 3);
133 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
136 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
141 static const struct clkops clk_pxa27x_mem_ops = {
142 .enable = clk_dummy_enable,
143 .disable = clk_dummy_disable,
144 .getrate = clk_pxa27x_mem_getrate,
148 * Return the current LCD clock frequency in units of 10kHz as
150 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
153 unsigned int l, L, k, K;
158 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
166 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
168 return pxa27x_get_lcdclk_frequency_10khz() * 10000;
171 static const struct clkops clk_pxa27x_lcd_ops = {
172 .enable = clk_pxa2xx_cken_enable,
173 .disable = clk_pxa2xx_cken_disable,
174 .getrate = clk_pxa27x_lcd_getrate,
177 static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
178 static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
179 static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
180 static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
181 static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
182 static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
183 static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
184 static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
185 static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
186 static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
187 static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
188 static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
189 static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
190 static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
191 static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
192 static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
193 static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
194 static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
195 static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
196 static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
197 static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
198 static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
199 static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
201 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
202 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
203 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
205 static struct clk_lookup pxa27x_clkregs[] = {
206 INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
207 INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
208 INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
209 INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
210 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
211 INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
212 INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
213 INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
214 INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
215 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
216 INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
217 INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
218 INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
219 INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
220 INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
221 INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
222 INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
223 INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
224 INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
225 INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
226 INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
227 INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
228 INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
229 INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
230 INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
231 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
232 INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
233 INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
234 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
239 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
240 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
243 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
245 static unsigned int pwrmode = PWRMODE_SLEEP;
247 int __init pxa27x_set_pwrmode(unsigned int mode)
251 case PWRMODE_DEEPSLEEP:
260 * List of global PXA peripheral registers to preserve.
261 * More ones like CP and general purpose register values are preserved
262 * with the stack pointer in sleep.S.
271 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
273 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
279 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
281 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
284 PSSR = PSSR_RDH | PSSR_PH;
289 void pxa27x_cpu_pm_enter(suspend_state_t state)
291 extern void pxa_cpu_standby(void);
292 #ifndef CONFIG_IWMMXT
295 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
298 /* ensure voltage-change sequencer not initiated, which hangs */
301 /* Clear edge-detect status register. */
304 /* Clear reset status */
305 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
308 case PM_SUSPEND_STANDBY:
312 cpu_suspend(pwrmode, pxa27x_finish_suspend);
313 #ifndef CONFIG_IWMMXT
314 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
320 static int pxa27x_cpu_pm_valid(suspend_state_t state)
322 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
325 static int pxa27x_cpu_pm_prepare(void)
327 /* set resume return address */
328 PSPR = virt_to_phys(cpu_resume);
332 static void pxa27x_cpu_pm_finish(void)
334 /* ensure not to come back here if it wasn't intended */
338 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
339 .save_count = SLEEP_SAVE_COUNT,
340 .save = pxa27x_cpu_pm_save,
341 .restore = pxa27x_cpu_pm_restore,
342 .valid = pxa27x_cpu_pm_valid,
343 .enter = pxa27x_cpu_pm_enter,
344 .prepare = pxa27x_cpu_pm_prepare,
345 .finish = pxa27x_cpu_pm_finish,
348 static void __init pxa27x_init_pm(void)
350 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
353 static inline void pxa27x_init_pm(void) {}
356 /* PXA27x: Various gpios can issue wakeup events. This logic only
357 * handles the simple cases, not the WEMUX2 and WEMUX3 options
359 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
361 int gpio = pxa_irq_to_gpio(d->irq);
364 if (gpio >= 0 && gpio < 128)
365 return gpio_set_wake(gpio, on);
367 if (d->irq == IRQ_KEYPAD)
368 return keypad_set_wake(on);
389 void __init pxa27x_init_irq(void)
391 pxa_init_irq(34, pxa27x_set_wake);
394 static struct map_desc pxa27x_io_desc[] __initdata = {
396 .virtual = (unsigned long)SMEMC_VIRT,
397 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
398 .length = 0x00200000,
401 .virtual = 0xfe000000,
402 .pfn = __phys_to_pfn(0x58000000),
403 .length = 0x00100000,
408 void __init pxa27x_map_io(void)
411 iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
412 pxa27x_get_clk_frequency_khz(1);
416 * device registration specific to PXA27x.
418 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
423 pxa_register_device(&pxa27x_device_i2c_power, info);
426 static struct platform_device *devices[] __initdata = {
431 &pxa_device_asoc_ssp1,
432 &pxa_device_asoc_ssp2,
433 &pxa_device_asoc_ssp3,
434 &pxa_device_asoc_platform,
444 static int __init pxa27x_init(void)
448 if (cpu_is_pxa27x()) {
452 clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
454 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
459 register_syscore_ops(&pxa_irq_syscore_ops);
460 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
461 register_syscore_ops(&pxa_gpio_syscore_ops);
462 register_syscore_ops(&pxa2xx_clock_syscore_ops);
464 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
470 postcore_initcall(pxa27x_init);