2 * linux/arch/arm/mach-pxa/pxa27x.c
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
8 * Code specific to PXA27x aka Bulverde.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
21 #include <mach/hardware.h>
23 #include <mach/irqs.h>
24 #include <mach/gpio.h>
25 #include <mach/pxa27x.h>
26 #include <mach/reset.h>
27 #include <mach/ohci.h>
36 void pxa27x_clear_otgph(void)
38 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
41 EXPORT_SYMBOL(pxa27x_clear_otgph);
43 static unsigned long ac97_reset_config[] = {
50 void pxa27x_assert_ac97reset(int reset_gpio, int on)
52 if (reset_gpio == 113)
53 pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
54 &ac97_reset_config[1], 1);
57 pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
58 &ac97_reset_config[3], 1);
60 EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
62 /* Crystal clock: 13MHz */
63 #define BASE_CLK 13000000
66 * Get the clock frequency as reflected by CCSR and the turbo flag.
67 * We assume these values have been applied via a fcs.
68 * If info is not 0 we also display the current settings.
70 unsigned int pxa27x_get_clk_frequency_khz(int info)
72 unsigned long ccsr, clkcfg;
73 unsigned int l, L, m, M, n2, N, S;
77 cccr_a = CCCR & (1 << 25);
79 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
80 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
81 t = clkcfg & (1 << 0);
82 ht = clkcfg & (1 << 2);
83 b = clkcfg & (1 << 3);
87 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
91 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
95 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
96 L / 1000000, (L % 1000000) / 10000, l );
97 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
98 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
100 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
101 M / 1000000, (M % 1000000) / 10000, m );
102 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
103 S / 1000000, (S % 1000000) / 10000 );
106 return (t) ? (N/1000) : (L/1000);
110 * Return the current mem clock frequency in units of 10kHz as
111 * reflected by CCCR[A], B, and L
113 unsigned int pxa27x_get_memclk_frequency_10khz(void)
115 unsigned long ccsr, clkcfg;
116 unsigned int l, L, m, M;
120 cccr_a = CCCR & (1 << 25);
122 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
123 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
124 b = clkcfg & (1 << 3);
127 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
130 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
136 * Return the current LCD clock frequency in units of 10kHz as
138 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
141 unsigned int l, L, k, K;
146 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
154 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
156 return pxa27x_get_lcdclk_frequency_10khz() * 10000;
159 static const struct clkops clk_pxa27x_lcd_ops = {
160 .enable = clk_cken_enable,
161 .disable = clk_cken_disable,
162 .getrate = clk_pxa27x_lcd_getrate,
165 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
166 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
167 static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
168 static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
169 static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
170 static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
171 static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
172 static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
173 static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
174 static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
175 static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
176 static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
177 static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
178 static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
179 static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
180 static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
181 static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
182 static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
183 static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
184 static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
185 static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
186 static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
187 static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
188 static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
189 static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
191 static struct clk_lookup pxa27x_clkregs[] = {
192 INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
193 INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
194 INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
195 INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
196 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
197 INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
198 INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
199 INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
200 INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
201 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
202 INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
203 INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
204 INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
205 INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
206 INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
207 INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
208 INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
209 INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
210 INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
211 INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
212 INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
213 INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
214 INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
215 INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
216 INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
217 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
222 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
223 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
226 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
228 static unsigned int pwrmode = PWRMODE_SLEEP;
230 int __init pxa27x_set_pwrmode(unsigned int mode)
234 case PWRMODE_DEEPSLEEP:
243 * List of global PXA peripheral registers to preserve.
244 * More ones like CP and general purpose register values are preserved
245 * with the stack pointer in sleep.S.
255 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
264 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
269 PSSR = PSSR_RDH | PSSR_PH;
275 void pxa27x_cpu_pm_enter(suspend_state_t state)
277 extern void pxa_cpu_standby(void);
279 /* ensure voltage-change sequencer not initiated, which hangs */
282 /* Clear edge-detect status register. */
285 /* Clear reset status */
286 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
289 case PM_SUSPEND_STANDBY:
293 pxa27x_cpu_suspend(pwrmode);
298 static int pxa27x_cpu_pm_valid(suspend_state_t state)
300 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
303 static int pxa27x_cpu_pm_prepare(void)
305 /* set resume return address */
306 PSPR = virt_to_phys(pxa_cpu_resume);
310 static void pxa27x_cpu_pm_finish(void)
312 /* ensure not to come back here if it wasn't intended */
316 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
317 .save_count = SLEEP_SAVE_COUNT,
318 .save = pxa27x_cpu_pm_save,
319 .restore = pxa27x_cpu_pm_restore,
320 .valid = pxa27x_cpu_pm_valid,
321 .enter = pxa27x_cpu_pm_enter,
322 .prepare = pxa27x_cpu_pm_prepare,
323 .finish = pxa27x_cpu_pm_finish,
326 static void __init pxa27x_init_pm(void)
328 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
331 static inline void pxa27x_init_pm(void) {}
334 /* PXA27x: Various gpios can issue wakeup events. This logic only
335 * handles the simple cases, not the WEMUX2 and WEMUX3 options
337 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
339 int gpio = IRQ_TO_GPIO(irq);
342 if (gpio >= 0 && gpio < 128)
343 return gpio_set_wake(gpio, on);
345 if (irq == IRQ_KEYPAD)
346 return keypad_set_wake(on);
367 void __init pxa27x_init_irq(void)
369 pxa_init_irq(34, pxa27x_set_wake);
370 pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
374 * device registration specific to PXA27x.
376 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
381 pxa_register_device(&pxa27x_device_i2c_power, info);
384 static struct platform_device *devices[] __initdata = {
388 &pxa_device_asoc_ssp1,
389 &pxa_device_asoc_ssp2,
390 &pxa_device_asoc_ssp3,
391 &pxa_device_asoc_platform,
401 static struct sys_device pxa27x_sysdev[] = {
403 .cls = &pxa_irq_sysclass,
405 .cls = &pxa2xx_mfp_sysclass,
407 .cls = &pxa_gpio_sysclass,
411 static int __init pxa27x_init(void)
415 if (cpu_is_pxa27x()) {
419 clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
421 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
426 for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
427 ret = sysdev_register(&pxa27x_sysdev[i]);
429 pr_err("failed to register sysdev[%d]\n", i);
432 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
438 postcore_initcall(pxa27x_init);