2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/irq.h>
22 #include <linux/syscore_ops.h>
23 #include <linux/i2c/pxa-i2c.h>
25 #include <asm/mach/map.h>
26 #include <asm/suspend.h>
27 #include <mach/hardware.h>
28 #include <mach/pxa3xx-regs.h>
29 #include <mach/reset.h>
30 #include <mach/ohci.h>
33 #include <mach/smemc.h>
39 #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
40 #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
42 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
43 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
44 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
45 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
46 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
47 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
48 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
49 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
50 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
51 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
52 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
53 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
54 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
55 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
56 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
57 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
58 static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
60 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
61 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
62 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
63 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
64 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
66 static struct clk_lookup pxa3xx_clkregs[] = {
67 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
68 /* Power I2C clock is always on */
69 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
70 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
71 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
72 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
73 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
74 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
75 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
76 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
77 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
78 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
79 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
80 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
81 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
82 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
83 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
84 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
85 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
86 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
87 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
88 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
89 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
90 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
91 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
92 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
97 #define ISRAM_START 0x5c000000
98 #define ISRAM_SIZE SZ_256K
100 static void __iomem *sram;
101 static unsigned long wakeup_src;
104 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
105 * memory controller has to be reinitialised, so we place some code
106 * in the SRAM to perform this function.
108 * We disable FIQs across the standby - otherwise, we might receive a
109 * FIQ while the SDRAM is unavailable.
111 static void pxa3xx_cpu_standby(unsigned int pwrmode)
113 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
114 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
116 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
117 pm_enter_standby_end - pm_enter_standby_start);
121 AD2D0ER = wakeup_src;
135 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
136 * PXA3xx development kits assumes that the resuming process continues
137 * with the address stored within the first 4 bytes of SDRAM. The PSPR
138 * register is used privately by BootROM and OBM, and _must_ be set to
139 * 0x5c014000 for the moment.
141 static void pxa3xx_cpu_pm_suspend(void)
143 volatile unsigned long *p = (volatile void *)0xc0000000;
144 unsigned long saved_data = *p;
145 #ifndef CONFIG_IWMMXT
148 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
151 extern int pxa3xx_finish_suspend(unsigned long);
153 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
154 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
155 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
157 /* clear and setup wakeup source */
163 PCFR |= (1u << 13); /* L1_DIS */
164 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
168 /* overwrite with the resume address */
169 *p = virt_to_phys(cpu_resume);
171 cpu_suspend(0, pxa3xx_finish_suspend);
177 #ifndef CONFIG_IWMMXT
178 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
182 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
185 * Don't sleep if no wakeup sources are defined
187 if (wakeup_src == 0) {
188 printk(KERN_ERR "Not suspending: no wakeup sources\n");
193 case PM_SUSPEND_STANDBY:
194 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
198 pxa3xx_cpu_pm_suspend();
203 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
205 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
208 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
209 .valid = pxa3xx_cpu_pm_valid,
210 .enter = pxa3xx_cpu_pm_enter,
213 static void __init pxa3xx_init_pm(void)
215 sram = ioremap(ISRAM_START, ISRAM_SIZE);
217 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
222 * Since we copy wakeup code into the SRAM, we need to ensure
223 * that it is preserved over the low power modes. Note: bit 8
224 * is undocumented in the developer manual, but must be set.
226 AD1R |= ADXR_L2 | ADXR_R0;
227 AD2R |= ADXR_L2 | ADXR_R0;
228 AD3R |= ADXR_L2 | ADXR_R0;
231 * Clear the resume enable registers.
238 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
241 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
243 unsigned long flags, mask = 0;
247 mask = ADXER_MFP_WSSP3;
260 mask = ADXER_MFP_WAC97;
266 mask = ADXER_MFP_WSSP2;
269 mask = ADXER_MFP_WI2C;
272 mask = ADXER_MFP_WUART3;
275 mask = ADXER_MFP_WUART2;
278 mask = ADXER_MFP_WUART1;
281 mask = ADXER_MFP_WMMC1;
284 mask = ADXER_MFP_WSSP1;
290 mask = ADXER_MFP_WSSP4;
299 mask = ADXER_MFP_WMMC2;
302 mask = ADXER_MFP_WFLASH;
308 mask = ADXER_WEXTWAKE0;
311 mask = ADXER_WEXTWAKE1;
314 mask = ADXER_MFP_GEN12;
320 local_irq_save(flags);
325 local_irq_restore(flags);
330 static inline void pxa3xx_init_pm(void) {}
331 #define pxa3xx_set_wake NULL
334 static void pxa_ack_ext_wakeup(struct irq_data *d)
336 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
339 static void pxa_mask_ext_wakeup(struct irq_data *d)
342 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
345 static void pxa_unmask_ext_wakeup(struct irq_data *d)
348 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
351 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
353 if (flow_type & IRQ_TYPE_EDGE_RISING)
354 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
356 if (flow_type & IRQ_TYPE_EDGE_FALLING)
357 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
362 static struct irq_chip pxa_ext_wakeup_chip = {
364 .irq_ack = pxa_ack_ext_wakeup,
365 .irq_mask = pxa_mask_ext_wakeup,
366 .irq_unmask = pxa_unmask_ext_wakeup,
367 .irq_set_type = pxa_set_ext_wakeup_type,
370 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
375 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
376 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
378 set_irq_flags(irq, IRQF_VALID);
381 pxa_ext_wakeup_chip.irq_set_wake = fn;
384 void __init pxa3xx_init_irq(void)
386 /* enable CP6 access */
388 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
390 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
392 pxa_init_irq(56, pxa3xx_set_wake);
393 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
396 static struct map_desc pxa3xx_io_desc[] __initdata = {
398 .virtual = (unsigned long)SMEMC_VIRT,
399 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
400 .length = 0x00200000,
405 void __init pxa3xx_map_io(void)
408 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
409 pxa3xx_get_clk_frequency_khz(1);
413 * device registration specific to PXA3xx.
416 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
418 pxa_register_device(&pxa3xx_device_i2c_power, info);
421 static struct platform_device *devices[] __initdata = {
426 &pxa_device_asoc_ssp1,
427 &pxa_device_asoc_ssp2,
428 &pxa_device_asoc_ssp3,
429 &pxa_device_asoc_ssp4,
430 &pxa_device_asoc_platform,
441 static int __init pxa3xx_init(void)
445 if (cpu_is_pxa3xx()) {
450 * clear RDH bit every time after reset
452 * Note: the last 3 bits DxS are write-1-to-clear so carefully
453 * preserve them here in case they will be referenced later
455 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
457 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
459 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
464 register_syscore_ops(&pxa_irq_syscore_ops);
465 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
466 register_syscore_ops(&pxa3xx_clock_syscore_ops);
468 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
474 postcore_initcall(pxa3xx_init);