2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
23 #include <linux/sysdev.h>
25 #include <asm/hardware.h>
26 #include <asm/arch/pxa3xx-regs.h>
27 #include <asm/arch/ohci.h>
28 #include <asm/arch/pm.h>
29 #include <asm/arch/dma.h>
30 #include <asm/arch/ssp.h>
36 /* Crystal clock: 13MHz */
37 #define BASE_CLK 13000000
39 /* Ring Oscillator Clock: 60MHz */
40 #define RO_CLK 60000000
42 #define ACCR_D0CS (1 << 26)
44 /* crystal frequency to static memory controller multiplier (SMCFS) */
45 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
47 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
48 static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
51 * Get the clock frequency as reflected by CCSR and the turbo flag.
52 * We assume these values have been applied via a fcs.
53 * If info is not 0 we also display the current settings.
55 unsigned int pxa3xx_get_clk_frequency_khz(int info)
57 unsigned long acsr, xclkcfg;
58 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
60 /* Read XCLKCFG register turbo bit */
61 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
67 xn = (acsr >> 8) & 0x7;
68 hss = (acsr >> 14) & 0x3;
73 ro = acsr & ACCR_D0CS;
75 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
76 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
79 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
80 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
82 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
83 XL / 1000000, (XL % 1000000) / 10000, xl);
84 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
85 XN / 1000000, (XN % 1000000) / 10000, xn,
87 pr_info("HSIO bus clock: %d.%02dMHz\n",
88 HSS / 1000000, (HSS % 1000000) / 10000);
95 * Return the current static memory controller clock frequency
98 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
101 unsigned int smcfs, clk = 0;
105 smcfs = (acsr >> 23) & 0x7;
106 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
108 return (clk / 10000);
112 * Return the current HSIO bus clock frequency
114 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
117 unsigned int hss, hsio_clk;
121 hss = (acsr >> 14) & 0x3;
122 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
127 static void clk_pxa3xx_cken_enable(struct clk *clk)
129 unsigned long mask = 1ul << (clk->cken & 0x1f);
141 static void clk_pxa3xx_cken_disable(struct clk *clk)
143 unsigned long mask = 1ul << (clk->cken & 0x1f);
155 static const struct clkops clk_pxa3xx_cken_ops = {
156 .enable = clk_pxa3xx_cken_enable,
157 .disable = clk_pxa3xx_cken_disable,
160 static const struct clkops clk_pxa3xx_hsio_ops = {
161 .enable = clk_pxa3xx_cken_enable,
162 .disable = clk_pxa3xx_cken_disable,
163 .getrate = clk_pxa3xx_hsio_getrate,
166 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
170 .ops = &clk_pxa3xx_cken_ops, \
172 .cken = CKEN_##_cken, \
176 #define PXA3xx_CK(_name, _cken, _ops, _dev) \
181 .cken = CKEN_##_cken, \
184 static struct clk pxa3xx_clks[] = {
185 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
186 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
188 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
189 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
190 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
192 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
193 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
194 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
196 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
197 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
198 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
199 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
201 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
202 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
203 PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
207 #define SLEEP_SAVE_SIZE 4
209 #define ISRAM_START 0x5c000000
210 #define ISRAM_SIZE SZ_256K
212 static void __iomem *sram;
213 static unsigned long wakeup_src;
215 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
217 pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB);
219 if (CKENA & (1 << CKEN_USBH)) {
220 printk(KERN_ERR "PM: USB host clock not stopped?\n");
221 CKENA &= ~(1 << CKEN_USBH);
223 // CKENA |= 1 << (CKEN_ISC & 31);
226 * Low power modes require the HSIO2 clock to be enabled.
228 CKENB |= 1 << (CKEN_HSIO2 & 31);
231 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
233 CKENB &= ~(1 << (CKEN_HSIO2 & 31));
237 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
238 * memory controller has to be reinitialised, so we place some code
239 * in the SRAM to perform this function.
241 * We disable FIQs across the standby - otherwise, we might receive a
242 * FIQ while the SDRAM is unavailable.
244 static void pxa3xx_cpu_standby(unsigned int pwrmode)
246 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
247 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
249 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
250 pm_enter_standby_end - pm_enter_standby_start);
254 AD2D0ER = wakeup_src;
266 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
269 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
272 * Don't sleep if no wakeup sources are defined
278 case PM_SUSPEND_STANDBY:
279 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
287 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
289 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
292 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
293 .save_size = SLEEP_SAVE_SIZE,
294 .save = pxa3xx_cpu_pm_save,
295 .restore = pxa3xx_cpu_pm_restore,
296 .valid = pxa3xx_cpu_pm_valid,
297 .enter = pxa3xx_cpu_pm_enter,
300 static void __init pxa3xx_init_pm(void)
302 sram = ioremap(ISRAM_START, ISRAM_SIZE);
304 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
309 * Since we copy wakeup code into the SRAM, we need to ensure
310 * that it is preserved over the low power modes. Note: bit 8
311 * is undocumented in the developer manual, but must be set.
313 AD1R |= ADXR_L2 | ADXR_R0;
314 AD2R |= ADXR_L2 | ADXR_R0;
315 AD3R |= ADXR_L2 | ADXR_R0;
318 * Clear the resume enable registers.
325 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
328 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
330 unsigned long flags, mask = 0;
334 mask = ADXER_MFP_WSSP3;
347 mask = ADXER_MFP_WAC97;
353 mask = ADXER_MFP_WSSP2;
356 mask = ADXER_MFP_WI2C;
359 mask = ADXER_MFP_WUART3;
362 mask = ADXER_MFP_WUART2;
365 mask = ADXER_MFP_WUART1;
368 mask = ADXER_MFP_WMMC1;
371 mask = ADXER_MFP_WSSP1;
377 mask = ADXER_MFP_WSSP4;
386 mask = ADXER_MFP_WMMC2;
389 mask = ADXER_MFP_WFLASH;
395 mask = ADXER_WEXTWAKE0;
398 mask = ADXER_WEXTWAKE1;
401 mask = ADXER_MFP_GEN12;
405 local_irq_save(flags);
410 local_irq_restore(flags);
415 static void pxa3xx_init_irq_pm(void)
417 pxa_init_irq_set_wake(pxa3xx_set_wake);
421 static inline void pxa3xx_init_pm(void) {}
422 static inline void pxa3xx_init_irq_pm(void) {}
425 void __init pxa3xx_init_irq(void)
427 /* enable CP6 access */
429 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
431 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
435 pxa_init_irq_gpio(128);
436 pxa3xx_init_irq_pm();
440 * device registration specific to PXA3xx.
443 static struct platform_device *devices[] __initdata = {
456 static struct sys_device pxa3xx_sysdev[] = {
459 .cls = &pxa_irq_sysclass,
462 .cls = &pxa_irq_sysclass,
466 static int __init pxa3xx_init(void)
470 if (cpu_is_pxa3xx()) {
471 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
473 if ((ret = pxa_init_dma(32)))
478 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
479 ret = sysdev_register(&pxa3xx_sysdev[i]);
481 pr_err("failed to register sysdev[%d]\n", i);
484 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
490 subsys_initcall(pxa3xx_init);