2 * Copyright (C) 2002 ARM Ltd.
4 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/errno.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
17 #include <linux/of_address.h>
18 #include <linux/smp.h>
20 #include <linux/qcom_scm.h>
22 #include <asm/smp_plat.h>
25 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0
26 #define SCSS_CPU1CORE_RESET 0x2d80
27 #define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64
29 #define APCS_CPU_PWR_CTL 0x04
30 #define PLL_CLAMP BIT(8)
31 #define CORE_PWRD_UP BIT(7)
32 #define COREPOR_RST BIT(5)
33 #define CORE_RST BIT(4)
34 #define L2DT_SLP BIT(3)
37 #define APC_PWR_GATE_CTL 0x14
38 #define BHS_CNT_SHIFT 24
39 #define LDO_PWR_DWN_SHIFT 16
40 #define LDO_BYP_SHIFT 8
41 #define BHS_SEG_SHIFT 1
44 #define APCS_SAW2_VCTL 0x14
45 #define APCS_SAW2_2_VCTL 0x1c
47 extern void secondary_startup_arm(void);
49 static DEFINE_SPINLOCK(boot_lock);
51 #ifdef CONFIG_HOTPLUG_CPU
52 static void qcom_cpu_die(unsigned int cpu)
58 static void qcom_secondary_init(unsigned int cpu)
61 * Synchronise with the boot thread.
63 spin_lock(&boot_lock);
64 spin_unlock(&boot_lock);
67 static int scss_release_secondary(unsigned int cpu)
69 struct device_node *node;
72 node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
74 pr_err("%s: can't find node\n", __func__);
78 base = of_iomap(node, 0);
83 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
84 writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
85 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
92 static int kpssv1_release_secondary(unsigned int cpu)
95 void __iomem *reg, *saw_reg;
96 struct device_node *cpu_node, *acc_node, *saw_node;
99 cpu_node = of_get_cpu_node(cpu, NULL);
103 acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
109 saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
115 reg = of_iomap(acc_node, 0);
121 saw_reg = of_iomap(saw_node, 0);
127 /* Turn on CPU rail */
128 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
132 /* Krait bring-up sequence */
133 val = PLL_CLAMP | L2DT_SLP | CLAMP;
134 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
136 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
141 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
146 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
151 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
156 writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
163 of_node_put(saw_node);
165 of_node_put(acc_node);
167 of_node_put(cpu_node);
171 static int kpssv2_release_secondary(unsigned int cpu)
174 struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
175 void __iomem *l2_saw_base;
179 cpu_node = of_get_cpu_node(cpu, NULL);
183 acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
189 l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
195 saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
201 reg = of_iomap(acc_node, 0);
207 l2_saw_base = of_iomap(saw_node, 0);
213 /* Turn on the BHS, turn off LDO Bypass and power down LDO */
214 reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
215 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
217 /* wait for the BHS to settle */
220 /* Turn on BHS segments */
221 reg_val |= 0x3f << BHS_SEG_SHIFT;
222 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
224 /* wait for the BHS to settle */
227 /* Finally turn on the bypass so that BHS supplies power */
228 reg_val |= 0x3f << LDO_BYP_SHIFT;
229 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
231 /* enable max phases */
232 writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
236 reg_val = COREPOR_RST | CLAMP;
237 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
242 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
246 reg_val &= ~COREPOR_RST;
247 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
250 reg_val |= CORE_PWRD_UP;
251 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
256 iounmap(l2_saw_base);
260 of_node_put(saw_node);
262 of_node_put(l2_node);
264 of_node_put(acc_node);
266 of_node_put(cpu_node);
271 static DEFINE_PER_CPU(int, cold_boot_done);
273 static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
277 if (!per_cpu(cold_boot_done, cpu)) {
280 per_cpu(cold_boot_done, cpu) = true;
284 * set synchronisation state between this boot processor
285 * and the secondary one
287 spin_lock(&boot_lock);
290 * Send the secondary CPU a soft interrupt, thereby causing
291 * the boot monitor to read the system wide flags register,
292 * and branch to the address found there.
294 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
297 * now the secondary core is starting up let it run its
298 * calibrations, then wait for it to finish
300 spin_unlock(&boot_lock);
305 static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
307 return qcom_boot_secondary(cpu, scss_release_secondary);
310 static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
312 return qcom_boot_secondary(cpu, kpssv1_release_secondary);
315 static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
317 return qcom_boot_secondary(cpu, kpssv2_release_secondary);
320 static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
324 if (qcom_scm_set_cold_boot_addr(secondary_startup_arm,
326 for_each_present_cpu(cpu) {
327 if (cpu == smp_processor_id())
329 set_cpu_present(cpu, false);
331 pr_warn("Failed to set CPU boot address, disabling SMP\n");
335 static struct smp_operations smp_msm8660_ops __initdata = {
336 .smp_prepare_cpus = qcom_smp_prepare_cpus,
337 .smp_secondary_init = qcom_secondary_init,
338 .smp_boot_secondary = msm8660_boot_secondary,
339 #ifdef CONFIG_HOTPLUG_CPU
340 .cpu_die = qcom_cpu_die,
343 CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
345 static struct smp_operations qcom_smp_kpssv1_ops __initdata = {
346 .smp_prepare_cpus = qcom_smp_prepare_cpus,
347 .smp_secondary_init = qcom_secondary_init,
348 .smp_boot_secondary = kpssv1_boot_secondary,
349 #ifdef CONFIG_HOTPLUG_CPU
350 .cpu_die = qcom_cpu_die,
353 CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
355 static struct smp_operations qcom_smp_kpssv2_ops __initdata = {
356 .smp_prepare_cpus = qcom_smp_prepare_cpus,
357 .smp_secondary_init = qcom_secondary_init,
358 .smp_boot_secondary = kpssv2_boot_secondary,
359 #ifdef CONFIG_HOTPLUG_CPU
360 .cpu_die = qcom_cpu_die,
363 CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);