2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
29 #include <linux/smsc911x.h>
30 #include <linux/ata_platform.h>
31 #include <linux/amba/mmci.h>
32 #include <linux/gfp.h>
34 #include <asm/clkdev.h>
35 #include <asm/system.h>
36 #include <mach/hardware.h>
39 #include <asm/mach-types.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/flash.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/map.h>
48 #include <asm/hardware/gic.h>
50 #include <mach/clkdev.h>
51 #include <mach/platform.h>
52 #include <mach/irqs.h>
53 #include <plat/timer-sp.h>
57 /* used by entry-macro.S and platsmp.c */
58 void __iomem *gic_cpu_base_addr;
60 #ifdef CONFIG_ZONE_DMA
62 * Adjust the zones if there are restrictions for DMA access.
64 void __init realview_adjust_zones(int node, unsigned long *size,
67 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
69 if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
72 size[ZONE_NORMAL] = size[0] - dma_size;
73 size[ZONE_DMA] = dma_size;
74 hole[ZONE_NORMAL] = hole[0];
80 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
82 static int realview_flash_init(void)
86 val = __raw_readl(REALVIEW_FLASHCTRL);
87 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
88 __raw_writel(val, REALVIEW_FLASHCTRL);
93 static void realview_flash_exit(void)
97 val = __raw_readl(REALVIEW_FLASHCTRL);
98 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
99 __raw_writel(val, REALVIEW_FLASHCTRL);
102 static void realview_flash_set_vpp(int on)
106 val = __raw_readl(REALVIEW_FLASHCTRL);
108 val |= REALVIEW_FLASHPROG_FLVPPEN;
110 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
111 __raw_writel(val, REALVIEW_FLASHCTRL);
114 static struct flash_platform_data realview_flash_data = {
115 .map_name = "cfi_probe",
117 .init = realview_flash_init,
118 .exit = realview_flash_exit,
119 .set_vpp = realview_flash_set_vpp,
122 struct platform_device realview_flash_device = {
126 .platform_data = &realview_flash_data,
130 int realview_flash_register(struct resource *res, u32 num)
132 realview_flash_device.resource = res;
133 realview_flash_device.num_resources = num;
134 return platform_device_register(&realview_flash_device);
137 static struct smsc911x_platform_config smsc911x_config = {
138 .flags = SMSC911X_USE_32BIT,
139 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
140 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
141 .phy_interface = PHY_INTERFACE_MODE_MII,
144 static struct platform_device realview_eth_device = {
150 int realview_eth_register(const char *name, struct resource *res)
153 realview_eth_device.name = name;
154 realview_eth_device.resource = res;
155 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
156 realview_eth_device.dev.platform_data = &smsc911x_config;
158 return platform_device_register(&realview_eth_device);
161 struct platform_device realview_usb_device = {
166 int realview_usb_register(struct resource *res)
168 realview_usb_device.resource = res;
169 return platform_device_register(&realview_usb_device);
172 static struct pata_platform_info pata_platform_data = {
176 static struct resource pata_resources[] = {
178 .start = REALVIEW_CF_BASE,
179 .end = REALVIEW_CF_BASE + 0xff,
180 .flags = IORESOURCE_MEM,
183 .start = REALVIEW_CF_BASE + 0x100,
184 .end = REALVIEW_CF_BASE + SZ_4K - 1,
185 .flags = IORESOURCE_MEM,
189 struct platform_device realview_cf_device = {
190 .name = "pata_platform",
192 .num_resources = ARRAY_SIZE(pata_resources),
193 .resource = pata_resources,
195 .platform_data = &pata_platform_data,
199 static struct resource realview_i2c_resource = {
200 .start = REALVIEW_I2C_BASE,
201 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
202 .flags = IORESOURCE_MEM,
205 struct platform_device realview_i2c_device = {
206 .name = "versatile-i2c",
209 .resource = &realview_i2c_resource,
212 static struct i2c_board_info realview_i2c_board_info[] = {
214 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
218 static int __init realview_i2c_init(void)
220 return i2c_register_board_info(0, realview_i2c_board_info,
221 ARRAY_SIZE(realview_i2c_board_info));
223 arch_initcall(realview_i2c_init);
225 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
228 * This is only used if GPIOLIB support is disabled
230 static unsigned int realview_mmc_status(struct device *dev)
232 struct amba_device *adev = container_of(dev, struct amba_device, dev);
235 if (adev->res.start == REALVIEW_MMCI0_BASE)
240 return !(readl(REALVIEW_SYSMCI) & mask);
243 struct mmci_platform_data realview_mmc0_plat_data = {
244 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
245 .status = realview_mmc_status,
250 struct mmci_platform_data realview_mmc1_plat_data = {
251 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
252 .status = realview_mmc_status,
260 static const struct icst_params realview_oscvco_params = {
262 .vco_max = ICST307_VCO_MAX,
263 .vco_min = ICST307_VCO_MIN,
268 .s2div = icst307_s2div,
269 .idx2s = icst307_idx2s,
272 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
274 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
277 val = readl(clk->vcoreg) & ~0x7ffff;
278 val |= vco.v | (vco.r << 9) | (vco.s << 16);
280 writel(0xa05f, sys_lock);
281 writel(val, clk->vcoreg);
285 static const struct clk_ops oscvco_clk_ops = {
286 .round = icst_clk_round,
288 .setvco = realview_oscvco_set,
291 static struct clk oscvco_clk = {
292 .ops = &oscvco_clk_ops,
293 .params = &realview_oscvco_params,
297 * These are fixed clocks.
299 static struct clk ref24_clk = {
303 static struct clk dummy_apb_pclk;
305 static struct clk_lookup lookups[] = {
307 .con_id = "apb_pclk",
308 .clk = &dummy_apb_pclk,
310 .dev_id = "dev:uart0",
313 .dev_id = "dev:uart1",
316 .dev_id = "dev:uart2",
319 .dev_id = "fpga:uart3",
322 .dev_id = "fpga:kmi0",
325 .dev_id = "fpga:kmi1",
328 .dev_id = "fpga:mmc0",
331 .dev_id = "dev:clcd",
334 .dev_id = "issp:clcd",
339 static int __init clk_init(void)
341 if (machine_is_realview_pb1176())
342 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
344 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
346 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
350 arch_initcall(clk_init);
355 #define SYS_CLCD_NLCDIOON (1 << 2)
356 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
357 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
358 #define SYS_CLCD_ID_MASK (0x1f << 8)
359 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
360 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
361 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
362 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
363 #define SYS_CLCD_ID_VGA (0x1f << 8)
365 static struct clcd_panel vga = {
379 .vmode = FB_VMODE_NONINTERLACED,
383 .tim2 = TIM2_BCD | TIM2_IPC,
384 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
388 static struct clcd_panel xvga = {
402 .vmode = FB_VMODE_NONINTERLACED,
406 .tim2 = TIM2_BCD | TIM2_IPC,
407 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
411 static struct clcd_panel sanyo_3_8_in = {
413 .name = "Sanyo QVGA",
425 .vmode = FB_VMODE_NONINTERLACED,
430 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
434 static struct clcd_panel sanyo_2_5_in = {
436 .name = "Sanyo QVGA Portrait",
447 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
448 .vmode = FB_VMODE_NONINTERLACED,
452 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
453 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
457 static struct clcd_panel epson_2_2_in = {
459 .name = "Epson QCIF",
471 .vmode = FB_VMODE_NONINTERLACED,
475 .tim2 = TIM2_BCD | TIM2_IPC,
476 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
481 * Detect which LCD panel is connected, and return the appropriate
482 * clcd_panel structure. Note: we do not have any information on
483 * the required timings for the 8.4in panel, so we presently assume
486 static struct clcd_panel *realview_clcd_panel(void)
488 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
489 struct clcd_panel *vga_panel;
490 struct clcd_panel *panel;
493 if (machine_is_realview_eb())
498 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
499 if (val == SYS_CLCD_ID_SANYO_3_8)
500 panel = &sanyo_3_8_in;
501 else if (val == SYS_CLCD_ID_SANYO_2_5)
502 panel = &sanyo_2_5_in;
503 else if (val == SYS_CLCD_ID_EPSON_2_2)
504 panel = &epson_2_2_in;
505 else if (val == SYS_CLCD_ID_VGA)
508 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
517 * Disable all display connectors on the interface module.
519 static void realview_clcd_disable(struct clcd_fb *fb)
521 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
524 val = readl(sys_clcd);
525 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
526 writel(val, sys_clcd);
530 * Enable the relevant connector on the interface module.
532 static void realview_clcd_enable(struct clcd_fb *fb)
534 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
540 val = readl(sys_clcd);
541 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
542 writel(val, sys_clcd);
545 static int realview_clcd_setup(struct clcd_fb *fb)
547 unsigned long framesize;
550 if (machine_is_realview_eb())
552 framesize = 640 * 480 * 2;
555 framesize = 1024 * 768 * 2;
557 fb->panel = realview_clcd_panel();
559 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
560 &dma, GFP_KERNEL | GFP_DMA);
561 if (!fb->fb.screen_base) {
562 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
566 fb->fb.fix.smem_start = dma;
567 fb->fb.fix.smem_len = framesize;
572 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
574 return dma_mmap_writecombine(&fb->dev->dev, vma,
576 fb->fb.fix.smem_start,
577 fb->fb.fix.smem_len);
580 static void realview_clcd_remove(struct clcd_fb *fb)
582 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
583 fb->fb.screen_base, fb->fb.fix.smem_start);
586 struct clcd_board clcd_plat_data = {
588 .check = clcdfb_check,
589 .decode = clcdfb_decode,
590 .disable = realview_clcd_disable,
591 .enable = realview_clcd_enable,
592 .setup = realview_clcd_setup,
593 .mmap = realview_clcd_mmap,
594 .remove = realview_clcd_remove,
598 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
600 void realview_leds_event(led_event_t ledevt)
604 u32 led = 1 << smp_processor_id();
606 local_irq_save(flags);
607 val = readl(VA_LEDS_BASE);
619 val = val ^ REALVIEW_SYS_LED7;
630 writel(val, VA_LEDS_BASE);
631 local_irq_restore(flags);
633 #endif /* CONFIG_LEDS */
636 * Where is the timer (VA)?
638 void __iomem *timer0_va_base;
639 void __iomem *timer1_va_base;
640 void __iomem *timer2_va_base;
641 void __iomem *timer3_va_base;
644 * Set up the clock source and clock events devices
646 void __init realview_timer_init(unsigned int timer_irq)
651 * set clock frequency:
652 * REALVIEW_REFCLK is 32KHz
653 * REALVIEW_TIMCLK is 1MHz
655 val = readl(__io_address(REALVIEW_SCTL_BASE));
656 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
657 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
658 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
659 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
660 __io_address(REALVIEW_SCTL_BASE));
663 * Initialise to a known state (all timers off)
665 writel(0, timer0_va_base + TIMER_CTRL);
666 writel(0, timer1_va_base + TIMER_CTRL);
667 writel(0, timer2_va_base + TIMER_CTRL);
668 writel(0, timer3_va_base + TIMER_CTRL);
670 sp804_clocksource_init(timer3_va_base);
671 sp804_clockevents_init(timer0_va_base, timer_irq);
675 * Setup the memory banks.
677 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
678 struct meminfo *meminfo)
681 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
682 * Half of this is mirrored at 0.
684 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
685 meminfo->bank[0].start = 0x70000000;
686 meminfo->bank[0].size = SZ_512M;
687 meminfo->nr_banks = 1;
689 meminfo->bank[0].start = 0;
690 meminfo->bank[0].size = SZ_256M;
691 meminfo->nr_banks = 1;