arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/io.h>
  29 #include <linux/smsc911x.h>
  30 #include <linux/ata_platform.h>
  31 #include <linux/amba/mmci.h>
  32
  33 #include <asm/clkdev.h>
  34 #include <asm/system.h>
  35 #include <mach/hardware.h>
  36 #include <asm/irq.h>
  37 #include <asm/leds.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/icst.h>
  41
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/flash.h>
  44 #include <asm/mach/irq.h>
  45 #include <asm/mach/map.h>
  46
  47 #include <asm/hardware/gic.h>
  48
  49 #include <mach/clkdev.h>
  50 #include <mach/platform.h>
  51 #include <mach/irqs.h>
  52 #include <plat/timer-sp.h>
  53
  54 #include "core.h"
  55
  56 /* used by entry-macro.S and platsmp.c */
  57 void __iomem *gic_cpu_base_addr;
  58
  59 #ifdef CONFIG_ZONE_DMA
  60 /*
  61  * Adjust the zones if there are restrictions for DMA access.
  62  */
  63 void __init realview_adjust_zones(int node, unsigned long *size,
  64                                   unsigned long *hole)
  65 {
  66         unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
  67
  68         if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
  69                 return;
  70
  71         size[ZONE_NORMAL] = size[0] - dma_size;
  72         size[ZONE_DMA] = dma_size;
  73         hole[ZONE_NORMAL] = hole[0];
  74         hole[ZONE_DMA] = 0;
  75 }
  76 #endif
  77
  78
  79 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  80
  81 static int realview_flash_init(void)
  82 {
  83         u32 val;
  84
  85         val = __raw_readl(REALVIEW_FLASHCTRL);
  86         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  87         __raw_writel(val, REALVIEW_FLASHCTRL);
  88
  89         return 0;
  90 }
  91
  92 static void realview_flash_exit(void)
  93 {
  94         u32 val;
  95
  96         val = __raw_readl(REALVIEW_FLASHCTRL);
  97         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  98         __raw_writel(val, REALVIEW_FLASHCTRL);
  99 }
 100
 101 static void realview_flash_set_vpp(int on)
 102 {
 103         u32 val;
 104
 105         val = __raw_readl(REALVIEW_FLASHCTRL);
 106         if (on)
 107                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 108         else
 109                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 110         __raw_writel(val, REALVIEW_FLASHCTRL);
 111 }
 112
 113 static struct flash_platform_data realview_flash_data = {
 114         .map_name               = "cfi_probe",
 115         .width                  = 4,
 116         .init                   = realview_flash_init,
 117         .exit                   = realview_flash_exit,
 118         .set_vpp                = realview_flash_set_vpp,
 119 };
 120
 121 struct platform_device realview_flash_device = {
 122         .name                   = "armflash",
 123         .id                     = 0,
 124         .dev                    = {
 125                 .platform_data  = &realview_flash_data,
 126         },
 127 };
 128
 129 int realview_flash_register(struct resource *res, u32 num)
 130 {
 131         realview_flash_device.resource = res;
 132         realview_flash_device.num_resources = num;
 133         return platform_device_register(&realview_flash_device);
 134 }
 135
 136 static struct smsc911x_platform_config smsc911x_config = {
 137         .flags          = SMSC911X_USE_32BIT,
 138         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 139         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 140         .phy_interface  = PHY_INTERFACE_MODE_MII,
 141 };
 142
 143 static struct platform_device realview_eth_device = {
 144         .name           = "smsc911x",
 145         .id             = 0,
 146         .num_resources  = 2,
 147 };
 148
 149 int realview_eth_register(const char *name, struct resource *res)
 150 {
 151         if (name)
 152                 realview_eth_device.name = name;
 153         realview_eth_device.resource = res;
 154         if (strcmp(realview_eth_device.name, "smsc911x") == 0)
 155                 realview_eth_device.dev.platform_data = &smsc911x_config;
 156
 157         return platform_device_register(&realview_eth_device);
 158 }
 159
 160 struct platform_device realview_usb_device = {
 161         .name                   = "isp1760",
 162         .num_resources          = 2,
 163 };
 164
 165 int realview_usb_register(struct resource *res)
 166 {
 167         realview_usb_device.resource = res;
 168         return platform_device_register(&realview_usb_device);
 169 }
 170
 171 static struct pata_platform_info pata_platform_data = {
 172         .ioport_shift           = 1,
 173 };
 174
 175 static struct resource pata_resources[] = {
 176         [0] = {
 177                 .start          = REALVIEW_CF_BASE,
 178                 .end            = REALVIEW_CF_BASE + 0xff,
 179                 .flags          = IORESOURCE_MEM,
 180         },
 181         [1] = {
 182                 .start          = REALVIEW_CF_BASE + 0x100,
 183                 .end            = REALVIEW_CF_BASE + SZ_4K - 1,
 184                 .flags          = IORESOURCE_MEM,
 185         },
 186 };
 187
 188 struct platform_device realview_cf_device = {
 189         .name                   = "pata_platform",
 190         .id                     = -1,
 191         .num_resources          = ARRAY_SIZE(pata_resources),
 192         .resource               = pata_resources,
 193         .dev                    = {
 194                 .platform_data  = &pata_platform_data,
 195         },
 196 };
 197
 198 static struct resource realview_i2c_resource = {
 199         .start          = REALVIEW_I2C_BASE,
 200         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 201         .flags          = IORESOURCE_MEM,
 202 };
 203
 204 struct platform_device realview_i2c_device = {
 205         .name           = "versatile-i2c",
 206         .id             = 0,
 207         .num_resources  = 1,
 208         .resource       = &realview_i2c_resource,
 209 };
 210
 211 static struct i2c_board_info realview_i2c_board_info[] = {
 212         {
 213                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 214         },
 215 };
 216
 217 static int __init realview_i2c_init(void)
 218 {
 219         return i2c_register_board_info(0, realview_i2c_board_info,
 220                                        ARRAY_SIZE(realview_i2c_board_info));
 221 }
 222 arch_initcall(realview_i2c_init);
 223
 224 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 225
 226 /*
 227  * This is only used if GPIOLIB support is disabled
 228  */
 229 static unsigned int realview_mmc_status(struct device *dev)
 230 {
 231         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 232         u32 mask;
 233
 234         if (adev->res.start == REALVIEW_MMCI0_BASE)
 235                 mask = 1;
 236         else
 237                 mask = 2;
 238
 239         return readl(REALVIEW_SYSMCI) & mask;
 240 }
 241
 242 struct mmci_platform_data realview_mmc0_plat_data = {
 243         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 244         .status         = realview_mmc_status,
 245         .gpio_wp        = 17,
 246         .gpio_cd        = 16,
 247 };
 248
 249 struct mmci_platform_data realview_mmc1_plat_data = {
 250         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 251         .status         = realview_mmc_status,
 252         .gpio_wp        = 19,
 253         .gpio_cd        = 18,
 254 };
 255
 256 /*
 257  * Clock handling
 258  */
 259 static const struct icst_params realview_oscvco_params = {
 260         .ref            = 24000000,
 261         .vco_max        = ICST307_VCO_MAX,
 262         .vco_min        = ICST307_VCO_MIN,
 263         .vd_min         = 4 + 8,
 264         .vd_max         = 511 + 8,
 265         .rd_min         = 1 + 2,
 266         .rd_max         = 127 + 2,
 267         .s2div          = icst307_s2div,
 268         .idx2s          = icst307_idx2s,
 269 };
 270
 271 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
 272 {
 273         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 274         void __iomem *sys_osc;
 275         u32 val;
 276
 277         if (machine_is_realview_pb1176())
 278                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 279         else
 280                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 281
 282         val = readl(sys_osc) & ~0x7ffff;
 283         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 284
 285         writel(0xa05f, sys_lock);
 286         writel(val, sys_osc);
 287         writel(0, sys_lock);
 288 }
 289
 290 static struct clk oscvco_clk = {
 291         .params = &realview_oscvco_params,
 292         .setvco = realview_oscvco_set,
 293 };
 294
 295 /*
 296  * These are fixed clocks.
 297  */
 298 static struct clk ref24_clk = {
 299         .rate   = 24000000,
 300 };
 301
 302 static struct clk_lookup lookups[] = {
 303         {       /* UART0 */
 304                 .dev_id         = "dev:uart0",
 305                 .clk            = &ref24_clk,
 306         }, {    /* UART1 */
 307                 .dev_id         = "dev:uart1",
 308                 .clk            = &ref24_clk,
 309         }, {    /* UART2 */
 310                 .dev_id         = "dev:uart2",
 311                 .clk            = &ref24_clk,
 312         }, {    /* UART3 */
 313                 .dev_id         = "fpga:uart3",
 314                 .clk            = &ref24_clk,
 315         }, {    /* KMI0 */
 316                 .dev_id         = "fpga:kmi0",
 317                 .clk            = &ref24_clk,
 318         }, {    /* KMI1 */
 319                 .dev_id         = "fpga:kmi1",
 320                 .clk            = &ref24_clk,
 321         }, {    /* MMC0 */
 322                 .dev_id         = "fpga:mmc0",
 323                 .clk            = &ref24_clk,
 324         }, {    /* EB:CLCD */
 325                 .dev_id         = "dev:clcd",
 326                 .clk            = &oscvco_clk,
 327         }, {    /* PB:CLCD */
 328                 .dev_id         = "issp:clcd",
 329                 .clk            = &oscvco_clk,
 330         }
 331 };
 332
 333 static int __init clk_init(void)
 334 {
 335         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 336         return 0;
 337 }
 338 arch_initcall(clk_init);
 339
 340 /*
 341  * CLCD support.
 342  */
 343 #define SYS_CLCD_NLCDIOON       (1 << 2)
 344 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 345 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 346 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 347 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 348 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 349 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 350 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 351 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 352
 353 static struct clcd_panel vga = {
 354         .mode           = {
 355                 .name           = "VGA",
 356                 .refresh        = 60,
 357                 .xres           = 640,
 358                 .yres           = 480,
 359                 .pixclock       = 39721,
 360                 .left_margin    = 40,
 361                 .right_margin   = 24,
 362                 .upper_margin   = 32,
 363                 .lower_margin   = 11,
 364                 .hsync_len      = 96,
 365                 .vsync_len      = 2,
 366                 .sync           = 0,
 367                 .vmode          = FB_VMODE_NONINTERLACED,
 368         },
 369         .width          = -1,
 370         .height         = -1,
 371         .tim2           = TIM2_BCD | TIM2_IPC,
 372         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 373         .bpp            = 16,
 374 };
 375
 376 static struct clcd_panel xvga = {
 377         .mode           = {
 378                 .name           = "XVGA",
 379                 .refresh        = 60,
 380                 .xres           = 1024,
 381                 .yres           = 768,
 382                 .pixclock       = 15748,
 383                 .left_margin    = 152,
 384                 .right_margin   = 48,
 385                 .upper_margin   = 23,
 386                 .lower_margin   = 3,
 387                 .hsync_len      = 104,
 388                 .vsync_len      = 4,
 389                 .sync           = 0,
 390                 .vmode          = FB_VMODE_NONINTERLACED,
 391         },
 392         .width          = -1,
 393         .height         = -1,
 394         .tim2           = TIM2_BCD | TIM2_IPC,
 395         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 396         .bpp            = 16,
 397 };
 398
 399 static struct clcd_panel sanyo_3_8_in = {
 400         .mode           = {
 401                 .name           = "Sanyo QVGA",
 402                 .refresh        = 116,
 403                 .xres           = 320,
 404                 .yres           = 240,
 405                 .pixclock       = 100000,
 406                 .left_margin    = 6,
 407                 .right_margin   = 6,
 408                 .upper_margin   = 5,
 409                 .lower_margin   = 5,
 410                 .hsync_len      = 6,
 411                 .vsync_len      = 6,
 412                 .sync           = 0,
 413                 .vmode          = FB_VMODE_NONINTERLACED,
 414         },
 415         .width          = -1,
 416         .height         = -1,
 417         .tim2           = TIM2_BCD,
 418         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 419         .bpp            = 16,
 420 };
 421
 422 static struct clcd_panel sanyo_2_5_in = {
 423         .mode           = {
 424                 .name           = "Sanyo QVGA Portrait",
 425                 .refresh        = 116,
 426                 .xres           = 240,
 427                 .yres           = 320,
 428                 .pixclock       = 100000,
 429                 .left_margin    = 20,
 430                 .right_margin   = 10,
 431                 .upper_margin   = 2,
 432                 .lower_margin   = 2,
 433                 .hsync_len      = 10,
 434                 .vsync_len      = 2,
 435                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 436                 .vmode          = FB_VMODE_NONINTERLACED,
 437         },
 438         .width          = -1,
 439         .height         = -1,
 440         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 441         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 442         .bpp            = 16,
 443 };
 444
 445 static struct clcd_panel epson_2_2_in = {
 446         .mode           = {
 447                 .name           = "Epson QCIF",
 448                 .refresh        = 390,
 449                 .xres           = 176,
 450                 .yres           = 220,
 451                 .pixclock       = 62500,
 452                 .left_margin    = 3,
 453                 .right_margin   = 2,
 454                 .upper_margin   = 1,
 455                 .lower_margin   = 0,
 456                 .hsync_len      = 3,
 457                 .vsync_len      = 2,
 458                 .sync           = 0,
 459                 .vmode          = FB_VMODE_NONINTERLACED,
 460         },
 461         .width          = -1,
 462         .height         = -1,
 463         .tim2           = TIM2_BCD | TIM2_IPC,
 464         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 465         .bpp            = 16,
 466 };
 467
 468 /*
 469  * Detect which LCD panel is connected, and return the appropriate
 470  * clcd_panel structure.  Note: we do not have any information on
 471  * the required timings for the 8.4in panel, so we presently assume
 472  * VGA timings.
 473  */
 474 static struct clcd_panel *realview_clcd_panel(void)
 475 {
 476         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 477         struct clcd_panel *vga_panel;
 478         struct clcd_panel *panel;
 479         u32 val;
 480
 481         if (machine_is_realview_eb())
 482                 vga_panel = &vga;
 483         else
 484                 vga_panel = &xvga;
 485
 486         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 487         if (val == SYS_CLCD_ID_SANYO_3_8)
 488                 panel = &sanyo_3_8_in;
 489         else if (val == SYS_CLCD_ID_SANYO_2_5)
 490                 panel = &sanyo_2_5_in;
 491         else if (val == SYS_CLCD_ID_EPSON_2_2)
 492                 panel = &epson_2_2_in;
 493         else if (val == SYS_CLCD_ID_VGA)
 494                 panel = vga_panel;
 495         else {
 496                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 497                         val);
 498                 panel = vga_panel;
 499         }
 500
 501         return panel;
 502 }
 503
 504 /*
 505  * Disable all display connectors on the interface module.
 506  */
 507 static void realview_clcd_disable(struct clcd_fb *fb)
 508 {
 509         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 510         u32 val;
 511
 512         val = readl(sys_clcd);
 513         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 514         writel(val, sys_clcd);
 515 }
 516
 517 /*
 518  * Enable the relevant connector on the interface module.
 519  */
 520 static void realview_clcd_enable(struct clcd_fb *fb)
 521 {
 522         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 523         u32 val;
 524
 525         /*
 526          * Enable the PSUs
 527          */
 528         val = readl(sys_clcd);
 529         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 530         writel(val, sys_clcd);
 531 }
 532
 533 static int realview_clcd_setup(struct clcd_fb *fb)
 534 {
 535         unsigned long framesize;
 536         dma_addr_t dma;
 537
 538         if (machine_is_realview_eb())
 539                 /* VGA, 16bpp */
 540                 framesize = 640 * 480 * 2;
 541         else
 542                 /* XVGA, 16bpp */
 543                 framesize = 1024 * 768 * 2;
 544
 545         fb->panel               = realview_clcd_panel();
 546
 547         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 548                                                     &dma, GFP_KERNEL | GFP_DMA);
 549         if (!fb->fb.screen_base) {
 550                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 551                 return -ENOMEM;
 552         }
 553
 554         fb->fb.fix.smem_start   = dma;
 555         fb->fb.fix.smem_len     = framesize;
 556
 557         return 0;
 558 }
 559
 560 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 561 {
 562         return dma_mmap_writecombine(&fb->dev->dev, vma,
 563                                      fb->fb.screen_base,
 564                                      fb->fb.fix.smem_start,
 565                                      fb->fb.fix.smem_len);
 566 }
 567
 568 static void realview_clcd_remove(struct clcd_fb *fb)
 569 {
 570         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 571                               fb->fb.screen_base, fb->fb.fix.smem_start);
 572 }
 573
 574 struct clcd_board clcd_plat_data = {
 575         .name           = "RealView",
 576         .check          = clcdfb_check,
 577         .decode         = clcdfb_decode,
 578         .disable        = realview_clcd_disable,
 579         .enable         = realview_clcd_enable,
 580         .setup          = realview_clcd_setup,
 581         .mmap           = realview_clcd_mmap,
 582         .remove         = realview_clcd_remove,
 583 };
 584
 585 #ifdef CONFIG_LEDS
 586 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 587
 588 void realview_leds_event(led_event_t ledevt)
 589 {
 590         unsigned long flags;
 591         u32 val;
 592         u32 led = 1 << smp_processor_id();
 593
 594         local_irq_save(flags);
 595         val = readl(VA_LEDS_BASE);
 596
 597         switch (ledevt) {
 598         case led_idle_start:
 599                 val = val & ~led;
 600                 break;
 601
 602         case led_idle_end:
 603                 val = val | led;
 604                 break;
 605
 606         case led_timer:
 607                 val = val ^ REALVIEW_SYS_LED7;
 608                 break;
 609
 610         case led_halted:
 611                 val = 0;
 612                 break;
 613
 614         default:
 615                 break;
 616         }
 617
 618         writel(val, VA_LEDS_BASE);
 619         local_irq_restore(flags);
 620 }
 621 #endif  /* CONFIG_LEDS */
 622
 623 /*
 624  * Where is the timer (VA)?
 625  */
 626 void __iomem *timer0_va_base;
 627 void __iomem *timer1_va_base;
 628 void __iomem *timer2_va_base;
 629 void __iomem *timer3_va_base;
 630
 631 /*
 632  * Set up the clock source and clock events devices
 633  */
 634 void __init realview_timer_init(unsigned int timer_irq)
 635 {
 636         u32 val;
 637
 638         /*
 639          * set clock frequency:
 640          *      REALVIEW_REFCLK is 32KHz
 641          *      REALVIEW_TIMCLK is 1MHz
 642          */
 643         val = readl(__io_address(REALVIEW_SCTL_BASE));
 644         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 645                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 646                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 647                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 648                __io_address(REALVIEW_SCTL_BASE));
 649
 650         /*
 651          * Initialise to a known state (all timers off)
 652          */
 653         writel(0, timer0_va_base + TIMER_CTRL);
 654         writel(0, timer1_va_base + TIMER_CTRL);
 655         writel(0, timer2_va_base + TIMER_CTRL);
 656         writel(0, timer3_va_base + TIMER_CTRL);
 657
 658         sp804_clocksource_init(timer3_va_base);
 659         sp804_clockevents_init(timer0_va_base, timer_irq);
 660 }
 661
 662 /*
 663  * Setup the memory banks.
 664  */
 665 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
 666                     struct meminfo *meminfo)
 667 {
 668         /*
 669          * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
 670          * Half of this is mirrored at 0.
 671          */
 672 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
 673         meminfo->bank[0].start = 0x70000000;
 674         meminfo->bank[0].size = SZ_512M;
 675         meminfo->nr_banks = 1;
 676 #else
 677         meminfo->bank[0].start = 0;
 678         meminfo->bank[0].size = SZ_256M;
 679         meminfo->nr_banks = 1;
 680 #endif
 681 }