2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
31 #include <linux/smsc911x.h>
32 #include <linux/ata_platform.h>
33 #include <linux/amba/mmci.h>
35 #include <asm/clkdev.h>
36 #include <asm/system.h>
37 #include <mach/hardware.h>
40 #include <asm/mach-types.h>
41 #include <asm/hardware/arm_timer.h>
42 #include <asm/hardware/icst307.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/flash.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/map.h>
49 #include <asm/hardware/gic.h>
51 #include <mach/platform.h>
52 #include <mach/irqs.h>
57 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
59 /* used by entry-macro.S and platsmp.c */
60 void __iomem *gic_cpu_base_addr;
62 #ifdef CONFIG_ZONE_DMA
64 * Adjust the zones if there are restrictions for DMA access.
66 void __init realview_adjust_zones(int node, unsigned long *size,
69 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
71 if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
74 size[ZONE_NORMAL] = size[0] - dma_size;
75 size[ZONE_DMA] = dma_size;
76 hole[ZONE_NORMAL] = hole[0];
82 * This is the RealView sched_clock implementation. This has
83 * a resolution of 41.7ns, and a maximum value of about 179s.
85 unsigned long long sched_clock(void)
89 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
96 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
98 static int realview_flash_init(void)
102 val = __raw_readl(REALVIEW_FLASHCTRL);
103 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
104 __raw_writel(val, REALVIEW_FLASHCTRL);
109 static void realview_flash_exit(void)
113 val = __raw_readl(REALVIEW_FLASHCTRL);
114 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
115 __raw_writel(val, REALVIEW_FLASHCTRL);
118 static void realview_flash_set_vpp(int on)
122 val = __raw_readl(REALVIEW_FLASHCTRL);
124 val |= REALVIEW_FLASHPROG_FLVPPEN;
126 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
127 __raw_writel(val, REALVIEW_FLASHCTRL);
130 static struct flash_platform_data realview_flash_data = {
131 .map_name = "cfi_probe",
133 .init = realview_flash_init,
134 .exit = realview_flash_exit,
135 .set_vpp = realview_flash_set_vpp,
138 struct platform_device realview_flash_device = {
142 .platform_data = &realview_flash_data,
146 int realview_flash_register(struct resource *res, u32 num)
148 realview_flash_device.resource = res;
149 realview_flash_device.num_resources = num;
150 return platform_device_register(&realview_flash_device);
153 static struct smsc911x_platform_config smsc911x_config = {
154 .flags = SMSC911X_USE_32BIT,
155 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
156 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
157 .phy_interface = PHY_INTERFACE_MODE_MII,
160 static struct platform_device realview_eth_device = {
166 int realview_eth_register(const char *name, struct resource *res)
169 realview_eth_device.name = name;
170 realview_eth_device.resource = res;
171 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
172 realview_eth_device.dev.platform_data = &smsc911x_config;
174 return platform_device_register(&realview_eth_device);
177 struct platform_device realview_usb_device = {
182 int realview_usb_register(struct resource *res)
184 realview_usb_device.resource = res;
185 return platform_device_register(&realview_usb_device);
188 static struct pata_platform_info pata_platform_data = {
192 static struct resource pata_resources[] = {
194 .start = REALVIEW_CF_BASE,
195 .end = REALVIEW_CF_BASE + 0xff,
196 .flags = IORESOURCE_MEM,
199 .start = REALVIEW_CF_BASE + 0x100,
200 .end = REALVIEW_CF_BASE + SZ_4K - 1,
201 .flags = IORESOURCE_MEM,
205 struct platform_device realview_cf_device = {
206 .name = "pata_platform",
208 .num_resources = ARRAY_SIZE(pata_resources),
209 .resource = pata_resources,
211 .platform_data = &pata_platform_data,
215 static struct resource realview_i2c_resource = {
216 .start = REALVIEW_I2C_BASE,
217 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
218 .flags = IORESOURCE_MEM,
221 struct platform_device realview_i2c_device = {
222 .name = "versatile-i2c",
225 .resource = &realview_i2c_resource,
228 static struct i2c_board_info realview_i2c_board_info[] = {
230 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
234 static int __init realview_i2c_init(void)
236 return i2c_register_board_info(0, realview_i2c_board_info,
237 ARRAY_SIZE(realview_i2c_board_info));
239 arch_initcall(realview_i2c_init);
241 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
244 * This is only used if GPIOLIB support is disabled
246 static unsigned int realview_mmc_status(struct device *dev)
248 struct amba_device *adev = container_of(dev, struct amba_device, dev);
251 if (adev->res.start == REALVIEW_MMCI0_BASE)
256 return readl(REALVIEW_SYSMCI) & mask;
259 struct mmci_platform_data realview_mmc0_plat_data = {
260 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
261 .status = realview_mmc_status,
266 struct mmci_platform_data realview_mmc1_plat_data = {
267 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
268 .status = realview_mmc_status,
276 static const struct icst307_params realview_oscvco_params = {
285 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
287 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
288 void __iomem *sys_osc;
291 if (machine_is_realview_pb1176())
292 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
294 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
296 val = readl(sys_osc) & ~0x7ffff;
297 val |= vco.v | (vco.r << 9) | (vco.s << 16);
299 writel(0xa05f, sys_lock);
300 writel(val, sys_osc);
304 static struct clk oscvco_clk = {
305 .params = &realview_oscvco_params,
306 .setvco = realview_oscvco_set,
310 * These are fixed clocks.
312 static struct clk ref24_clk = {
316 static struct clk_lookup lookups[] = {
318 .dev_id = "dev:uart0",
321 .dev_id = "dev:uart1",
324 .dev_id = "dev:uart2",
327 .dev_id = "fpga:uart3",
330 .dev_id = "fpga:kmi0",
333 .dev_id = "fpga:kmi1",
336 .dev_id = "fpga:mmc0",
339 .dev_id = "dev:clcd",
342 .dev_id = "issp:clcd",
347 static int __init clk_init(void)
351 for (i = 0; i < ARRAY_SIZE(lookups); i++)
352 clkdev_add(&lookups[i]);
355 arch_initcall(clk_init);
360 #define SYS_CLCD_NLCDIOON (1 << 2)
361 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
362 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
363 #define SYS_CLCD_ID_MASK (0x1f << 8)
364 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
365 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
366 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
367 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
368 #define SYS_CLCD_ID_VGA (0x1f << 8)
370 static struct clcd_panel vga = {
384 .vmode = FB_VMODE_NONINTERLACED,
388 .tim2 = TIM2_BCD | TIM2_IPC,
389 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
393 static struct clcd_panel xvga = {
407 .vmode = FB_VMODE_NONINTERLACED,
411 .tim2 = TIM2_BCD | TIM2_IPC,
412 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
416 static struct clcd_panel sanyo_3_8_in = {
418 .name = "Sanyo QVGA",
430 .vmode = FB_VMODE_NONINTERLACED,
435 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
439 static struct clcd_panel sanyo_2_5_in = {
441 .name = "Sanyo QVGA Portrait",
452 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
453 .vmode = FB_VMODE_NONINTERLACED,
457 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
458 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
462 static struct clcd_panel epson_2_2_in = {
464 .name = "Epson QCIF",
476 .vmode = FB_VMODE_NONINTERLACED,
480 .tim2 = TIM2_BCD | TIM2_IPC,
481 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
486 * Detect which LCD panel is connected, and return the appropriate
487 * clcd_panel structure. Note: we do not have any information on
488 * the required timings for the 8.4in panel, so we presently assume
491 static struct clcd_panel *realview_clcd_panel(void)
493 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
494 struct clcd_panel *vga_panel;
495 struct clcd_panel *panel;
498 if (machine_is_realview_eb())
503 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
504 if (val == SYS_CLCD_ID_SANYO_3_8)
505 panel = &sanyo_3_8_in;
506 else if (val == SYS_CLCD_ID_SANYO_2_5)
507 panel = &sanyo_2_5_in;
508 else if (val == SYS_CLCD_ID_EPSON_2_2)
509 panel = &epson_2_2_in;
510 else if (val == SYS_CLCD_ID_VGA)
513 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
522 * Disable all display connectors on the interface module.
524 static void realview_clcd_disable(struct clcd_fb *fb)
526 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
529 val = readl(sys_clcd);
530 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
531 writel(val, sys_clcd);
535 * Enable the relevant connector on the interface module.
537 static void realview_clcd_enable(struct clcd_fb *fb)
539 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
545 val = readl(sys_clcd);
546 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
547 writel(val, sys_clcd);
550 static int realview_clcd_setup(struct clcd_fb *fb)
552 unsigned long framesize;
555 if (machine_is_realview_eb())
557 framesize = 640 * 480 * 2;
560 framesize = 1024 * 768 * 2;
562 fb->panel = realview_clcd_panel();
564 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
565 &dma, GFP_KERNEL | GFP_DMA);
566 if (!fb->fb.screen_base) {
567 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
571 fb->fb.fix.smem_start = dma;
572 fb->fb.fix.smem_len = framesize;
577 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
579 return dma_mmap_writecombine(&fb->dev->dev, vma,
581 fb->fb.fix.smem_start,
582 fb->fb.fix.smem_len);
585 static void realview_clcd_remove(struct clcd_fb *fb)
587 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
588 fb->fb.screen_base, fb->fb.fix.smem_start);
591 struct clcd_board clcd_plat_data = {
593 .check = clcdfb_check,
594 .decode = clcdfb_decode,
595 .disable = realview_clcd_disable,
596 .enable = realview_clcd_enable,
597 .setup = realview_clcd_setup,
598 .mmap = realview_clcd_mmap,
599 .remove = realview_clcd_remove,
603 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
605 void realview_leds_event(led_event_t ledevt)
609 u32 led = 1 << smp_processor_id();
611 local_irq_save(flags);
612 val = readl(VA_LEDS_BASE);
624 val = val ^ REALVIEW_SYS_LED7;
635 writel(val, VA_LEDS_BASE);
636 local_irq_restore(flags);
638 #endif /* CONFIG_LEDS */
641 * Where is the timer (VA)?
643 void __iomem *timer0_va_base;
644 void __iomem *timer1_va_base;
645 void __iomem *timer2_va_base;
646 void __iomem *timer3_va_base;
649 * How long is the timer interval?
651 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
652 #if TIMER_INTERVAL >= 0x100000
653 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
654 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
655 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
656 #elif TIMER_INTERVAL >= 0x10000
657 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
658 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
659 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
661 #define TIMER_RELOAD (TIMER_INTERVAL)
662 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
663 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
666 static void timer_set_mode(enum clock_event_mode mode,
667 struct clock_event_device *clk)
672 case CLOCK_EVT_MODE_PERIODIC:
673 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
675 ctrl = TIMER_CTRL_PERIODIC;
676 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
678 case CLOCK_EVT_MODE_ONESHOT:
679 /* period set, and timer enabled in 'next_event' hook */
680 ctrl = TIMER_CTRL_ONESHOT;
681 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
683 case CLOCK_EVT_MODE_UNUSED:
684 case CLOCK_EVT_MODE_SHUTDOWN:
689 writel(ctrl, timer0_va_base + TIMER_CTRL);
692 static int timer_set_next_event(unsigned long evt,
693 struct clock_event_device *unused)
695 unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
697 writel(evt, timer0_va_base + TIMER_LOAD);
698 writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
703 static struct clock_event_device timer0_clockevent = {
706 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
707 .set_mode = timer_set_mode,
708 .set_next_event = timer_set_next_event,
710 .cpumask = cpu_all_mask,
713 static void __init realview_clockevents_init(unsigned int timer_irq)
715 timer0_clockevent.irq = timer_irq;
716 timer0_clockevent.mult =
717 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
718 timer0_clockevent.max_delta_ns =
719 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
720 timer0_clockevent.min_delta_ns =
721 clockevent_delta2ns(0xf, &timer0_clockevent);
723 clockevents_register_device(&timer0_clockevent);
727 * IRQ handler for the timer
729 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
731 struct clock_event_device *evt = &timer0_clockevent;
733 /* clear the interrupt */
734 writel(1, timer0_va_base + TIMER_INTCLR);
736 evt->event_handler(evt);
741 static struct irqaction realview_timer_irq = {
742 .name = "RealView Timer Tick",
743 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
744 .handler = realview_timer_interrupt,
747 static cycle_t realview_get_cycles(struct clocksource *cs)
749 return ~readl(timer3_va_base + TIMER_VALUE);
752 static struct clocksource clocksource_realview = {
755 .read = realview_get_cycles,
756 .mask = CLOCKSOURCE_MASK(32),
758 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
761 static void __init realview_clocksource_init(void)
763 /* setup timer 0 as free-running clocksource */
764 writel(0, timer3_va_base + TIMER_CTRL);
765 writel(0xffffffff, timer3_va_base + TIMER_LOAD);
766 writel(0xffffffff, timer3_va_base + TIMER_VALUE);
767 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
768 timer3_va_base + TIMER_CTRL);
770 clocksource_realview.mult =
771 clocksource_khz2mult(1000, clocksource_realview.shift);
772 clocksource_register(&clocksource_realview);
776 * Set up the clock source and clock events devices
778 void __init realview_timer_init(unsigned int timer_irq)
783 * set clock frequency:
784 * REALVIEW_REFCLK is 32KHz
785 * REALVIEW_TIMCLK is 1MHz
787 val = readl(__io_address(REALVIEW_SCTL_BASE));
788 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
789 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
790 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
791 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
792 __io_address(REALVIEW_SCTL_BASE));
795 * Initialise to a known state (all timers off)
797 writel(0, timer0_va_base + TIMER_CTRL);
798 writel(0, timer1_va_base + TIMER_CTRL);
799 writel(0, timer2_va_base + TIMER_CTRL);
800 writel(0, timer3_va_base + TIMER_CTRL);
803 * Make irqs happen for the system timer
805 setup_irq(timer_irq, &realview_timer_irq);
807 realview_clocksource_init();
808 realview_clockevents_init(timer_irq);
812 * Setup the memory banks.
814 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
815 struct meminfo *meminfo)
818 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
819 * Half of this is mirrored at 0.
821 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
822 meminfo->bank[0].start = 0x70000000;
823 meminfo->bank[0].size = SZ_512M;
824 meminfo->nr_banks = 1;
826 meminfo->bank[0].start = 0;
827 meminfo->bank[0].size = SZ_256M;
828 meminfo->nr_banks = 1;