2 * linux/arch/arm/mach-realview/realview_eb.c
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/platform_device.h>
24 #include <linux/sysdev.h>
25 #include <linux/amba/bus.h>
26 #include <linux/amba/pl061.h>
27 #include <linux/amba/mmci.h>
30 #include <mach/hardware.h>
33 #include <asm/mach-types.h>
35 #include <asm/pgtable.h>
36 #include <asm/hardware/gic.h>
37 #include <asm/hardware/cache-l2x0.h>
38 #include <asm/localtimer.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/time.h>
44 #include <mach/board-eb.h>
45 #include <mach/irqs.h>
49 static struct map_desc realview_eb_io_desc[] __initdata = {
51 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
52 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
56 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
57 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
61 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
62 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
66 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
67 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
71 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
72 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
76 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
77 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
81 #ifdef CONFIG_DEBUG_LL
83 .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
84 .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
91 static struct map_desc realview_eb11mp_io_desc[] __initdata = {
93 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
94 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
98 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
99 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
103 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
104 .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
110 static void __init realview_eb_map_io(void)
112 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
113 if (core_tile_eb11mp() || core_tile_a9mp())
114 iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
117 static struct pl061_platform_data gpio0_plat_data = {
122 static struct pl061_platform_data gpio1_plat_data = {
127 static struct pl061_platform_data gpio2_plat_data = {
133 * RealView EB AMBA devices
137 * These devices are connected via the core APB bridge
139 #define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ }
140 #define GPIO2_DMA { 0, 0 }
141 #define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ }
142 #define GPIO3_DMA { 0, 0 }
144 #define AACI_IRQ { IRQ_EB_AACI, NO_IRQ }
145 #define AACI_DMA { 0x80, 0x81 }
146 #define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
147 #define MMCI0_DMA { 0x84, 0 }
148 #define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ }
149 #define KMI0_DMA { 0, 0 }
150 #define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ }
151 #define KMI1_DMA { 0, 0 }
154 * These devices are connected directly to the multi-layer AHB switch
156 #define EB_SMC_IRQ { NO_IRQ, NO_IRQ }
157 #define EB_SMC_DMA { 0, 0 }
158 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
159 #define MPMC_DMA { 0, 0 }
160 #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
161 #define EB_CLCD_DMA { 0, 0 }
162 #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
163 #define DMAC_DMA { 0, 0 }
166 * These devices are connected via the core APB bridge
168 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
169 #define SCTL_DMA { 0, 0 }
170 #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
171 #define EB_WATCHDOG_DMA { 0, 0 }
172 #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
173 #define EB_GPIO0_DMA { 0, 0 }
174 #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
175 #define GPIO1_DMA { 0, 0 }
176 #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
177 #define EB_RTC_DMA { 0, 0 }
180 * These devices are connected via the DMA APB bridge
182 #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
183 #define SCI_DMA { 7, 6 }
184 #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
185 #define EB_UART0_DMA { 15, 14 }
186 #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
187 #define EB_UART1_DMA { 13, 12 }
188 #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
189 #define EB_UART2_DMA { 11, 10 }
190 #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
191 #define EB_UART3_DMA { 0x86, 0x87 }
192 #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
193 #define EB_SSP_DMA { 9, 8 }
195 /* FPGA Primecells */
196 AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
197 AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
198 AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
199 AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
200 AMBA_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
202 /* DevChip Primecells */
203 AMBA_DEVICE(smc, "dev:smc", EB_SMC, NULL);
204 AMBA_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data);
205 AMBA_DEVICE(dmac, "dev:dmac", DMAC, NULL);
206 AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL);
207 AMBA_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL);
208 AMBA_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
209 AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
210 AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
211 AMBA_DEVICE(rtc, "dev:rtc", EB_RTC, NULL);
212 AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL);
213 AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
214 AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
215 AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
216 AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, NULL);
218 static struct amba_device *amba_devs[] __initdata = {
241 * RealView EB platform devices
243 static struct resource realview_eb_flash_resource = {
244 .start = REALVIEW_EB_FLASH_BASE,
245 .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
246 .flags = IORESOURCE_MEM,
249 static struct resource realview_eb_eth_resources[] = {
251 .start = REALVIEW_EB_ETH_BASE,
252 .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
253 .flags = IORESOURCE_MEM,
258 .flags = IORESOURCE_IRQ,
263 * Detect and register the correct Ethernet device. RealView/EB rev D
264 * platforms use the newer SMSC LAN9118 Ethernet chip
266 static int eth_device_register(void)
268 void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
269 const char *name = NULL;
275 idrev = readl(eth_addr + 0x50);
276 if ((idrev & 0xFFFF0000) != 0x01180000)
277 /* SMSC LAN9118 not present, use LAN91C111 instead */
281 return realview_eth_register(name, realview_eb_eth_resources);
284 static struct resource realview_eb_isp1761_resources[] = {
286 .start = REALVIEW_EB_USB_BASE,
287 .end = REALVIEW_EB_USB_BASE + SZ_128K - 1,
288 .flags = IORESOURCE_MEM,
293 .flags = IORESOURCE_IRQ,
297 static struct resource pmu_resources[] = {
299 .start = IRQ_EB11MP_PMU_CPU0,
300 .end = IRQ_EB11MP_PMU_CPU0,
301 .flags = IORESOURCE_IRQ,
304 .start = IRQ_EB11MP_PMU_CPU1,
305 .end = IRQ_EB11MP_PMU_CPU1,
306 .flags = IORESOURCE_IRQ,
309 .start = IRQ_EB11MP_PMU_CPU2,
310 .end = IRQ_EB11MP_PMU_CPU2,
311 .flags = IORESOURCE_IRQ,
314 .start = IRQ_EB11MP_PMU_CPU3,
315 .end = IRQ_EB11MP_PMU_CPU3,
316 .flags = IORESOURCE_IRQ,
320 static struct platform_device pmu_device = {
322 .id = ARM_PMU_DEVICE_CPU,
323 .num_resources = ARRAY_SIZE(pmu_resources),
324 .resource = pmu_resources,
327 static void __init gic_init_irq(void)
329 if (core_tile_eb11mp() || core_tile_a9mp()) {
330 unsigned int pldctrl;
333 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
334 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
335 pldctrl |= 0x00800000;
336 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
337 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
339 /* core tile GIC, primary */
340 gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
341 gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
342 gic_cpu_init(0, gic_cpu_base_addr);
344 #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
345 /* board GIC, secondary */
346 gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
347 gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
348 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
351 /* board GIC, primary */
352 gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
353 gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
354 gic_cpu_init(0, gic_cpu_base_addr);
359 * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
361 static void realview_eb11mp_fixup(void)
364 dmac_device.irq[0] = IRQ_EB11MP_DMA;
365 uart0_device.irq[0] = IRQ_EB11MP_UART0;
366 uart1_device.irq[0] = IRQ_EB11MP_UART1;
367 uart2_device.irq[0] = IRQ_EB11MP_UART2;
368 uart3_device.irq[0] = IRQ_EB11MP_UART3;
369 clcd_device.irq[0] = IRQ_EB11MP_CLCD;
370 wdog_device.irq[0] = IRQ_EB11MP_WDOG;
371 gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
372 gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
373 gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
374 rtc_device.irq[0] = IRQ_EB11MP_RTC;
375 sci0_device.irq[0] = IRQ_EB11MP_SCI;
376 ssp0_device.irq[0] = IRQ_EB11MP_SSP;
377 aaci_device.irq[0] = IRQ_EB11MP_AACI;
378 mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
379 mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
380 kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
381 kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
383 /* platform devices */
384 realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
385 realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
386 realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB;
387 realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB;
390 static void __init realview_eb_timer_init(void)
392 unsigned int timer_irq;
394 timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
395 timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
396 timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
397 timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
399 if (core_tile_eb11mp() || core_tile_a9mp()) {
400 #ifdef CONFIG_LOCAL_TIMERS
401 twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE);
403 timer_irq = IRQ_EB11MP_TIMER0_1;
405 timer_irq = IRQ_EB_TIMER0_1;
407 realview_timer_init(timer_irq);
410 static struct sys_timer realview_eb_timer = {
411 .init = realview_eb_timer_init,
414 static void realview_eb_reset(char mode)
416 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
417 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
420 * To reset, we hit the on-board reset register
423 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
424 if (core_tile_eb11mp())
425 __raw_writel(0x0008, reset_ctrl);
428 static void __init realview_eb_init(void)
432 if (core_tile_eb11mp() || core_tile_a9mp()) {
433 realview_eb11mp_fixup();
435 #ifdef CONFIG_CACHE_L2X0
436 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
437 * Bits: .... ...0 0111 1001 0000 .... .... .... */
438 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
440 platform_device_register(&pmu_device);
443 realview_flash_register(&realview_eb_flash_resource, 1);
444 platform_device_register(&realview_i2c_device);
445 eth_device_register();
446 realview_usb_register(realview_eb_isp1761_resources);
448 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
449 struct amba_device *d = amba_devs[i];
450 amba_device_register(d, &iomem_resource);
454 leds_event = realview_leds_event;
456 realview_reset = realview_eb_reset;
459 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
460 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
461 .phys_io = REALVIEW_EB_UART0_BASE & SECTION_MASK,
462 .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
463 .boot_params = PHYS_OFFSET + 0x00000100,
464 .fixup = realview_fixup,
465 .map_io = realview_eb_map_io,
466 .init_irq = gic_init_irq,
467 .timer = &realview_eb_timer,
468 .init_machine = realview_eb_init,