arch/arm/mach-rpc/dma.c

   1 /*
   2  *  linux/arch/arm/mach-rpc/dma.c
   3  *
   4  *  Copyright (C) 1998 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  DMA functions specific to RiscPC architecture
  11  */
  12 #include <linux/slab.h>
  13 #include <linux/mman.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/page.h>
  20 #include <asm/dma.h>
  21 #include <asm/fiq.h>
  22 #include <asm/irq.h>
  23 #include <mach/hardware.h>
  24 #include <asm/uaccess.h>
  25
  26 #include <asm/mach/dma.h>
  27 #include <asm/hardware/iomd.h>
  28
  29 struct iomd_dma {
  30         struct dma_struct       dma;
  31         unsigned int            state;
  32         unsigned long           base;           /* Controller base address */
  33         int                     irq;            /* Controller IRQ */
  34         struct scatterlist      cur_sg;         /* Current controller buffer */
  35 };
  36
  37 #if 0
  38 typedef enum {
  39         dma_size_8      = 1,
  40         dma_size_16     = 2,
  41         dma_size_32     = 4,
  42         dma_size_128    = 16
  43 } dma_size_t;
  44 #endif
  45
  46 #define TRANSFER_SIZE   2
  47
  48 #define CURA    (0)
  49 #define ENDA    (IOMD_IO0ENDA - IOMD_IO0CURA)
  50 #define CURB    (IOMD_IO0CURB - IOMD_IO0CURA)
  51 #define ENDB    (IOMD_IO0ENDB - IOMD_IO0CURA)
  52 #define CR      (IOMD_IO0CR - IOMD_IO0CURA)
  53 #define ST      (IOMD_IO0ST - IOMD_IO0CURA)
  54
  55 static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma)
  56 {
  57         unsigned long end, offset, flags = 0;
  58
  59         if (idma->dma.sg) {
  60                 sg->dma_address = idma->dma.sg->dma_address;
  61                 offset = sg->dma_address & ~PAGE_MASK;
  62
  63                 end = offset + idma->dma.sg->length;
  64
  65                 if (end > PAGE_SIZE)
  66                         end = PAGE_SIZE;
  67
  68                 if (offset + TRANSFER_SIZE >= end)
  69                         flags |= DMA_END_L;
  70
  71                 sg->length = end - TRANSFER_SIZE;
  72
  73                 idma->dma.sg->length -= end - offset;
  74                 idma->dma.sg->dma_address += end - offset;
  75
  76                 if (idma->dma.sg->length == 0) {
  77                         if (idma->dma.sgcount > 1) {
  78                                 idma->dma.sg = sg_next(idma->dma.sg);
  79                                 idma->dma.sgcount--;
  80                         } else {
  81                                 idma->dma.sg = NULL;
  82                                 flags |= DMA_END_S;
  83                         }
  84                 }
  85         } else {
  86                 flags = DMA_END_S | DMA_END_L;
  87                 sg->dma_address = 0;
  88                 sg->length = 0;
  89         }
  90
  91         sg->length |= flags;
  92 }
  93
  94 static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
  95 {
  96         struct iomd_dma *idma = dev_id;
  97         unsigned long base = idma->base;
  98
  99         do {
 100                 unsigned int status;
 101
 102                 status = iomd_readb(base + ST);
 103                 if (!(status & DMA_ST_INT))
 104                         return IRQ_HANDLED;
 105
 106                 if ((idma->state ^ status) & DMA_ST_AB)
 107                         iomd_get_next_sg(&idma->cur_sg, idma);
 108
 109                 switch (status & (DMA_ST_OFL | DMA_ST_AB)) {
 110                 case DMA_ST_OFL:                        /* OIA */
 111                 case DMA_ST_AB:                         /* .IB */
 112                         iomd_writel(idma->cur_sg.dma_address, base + CURA);
 113                         iomd_writel(idma->cur_sg.length, base + ENDA);
 114                         idma->state = DMA_ST_AB;
 115                         break;
 116
 117                 case DMA_ST_OFL | DMA_ST_AB:            /* OIB */
 118                 case 0:                                 /* .IA */
 119                         iomd_writel(idma->cur_sg.dma_address, base + CURB);
 120                         iomd_writel(idma->cur_sg.length, base + ENDB);
 121                         idma->state = 0;
 122                         break;
 123                 }
 124
 125                 if (status & DMA_ST_OFL &&
 126                     idma->cur_sg.length == (DMA_END_S|DMA_END_L))
 127                         break;
 128         } while (1);
 129
 130         idma->state = ~DMA_ST_AB;
 131         disable_irq(irq);
 132
 133         return IRQ_HANDLED;
 134 }
 135
 136 static int iomd_request_dma(unsigned int chan, dma_t *dma)
 137 {
 138         struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
 139
 140         return request_irq(idma->irq, iomd_dma_handle,
 141                            IRQF_DISABLED, idma->dma.device_id, idma);
 142 }
 143
 144 static void iomd_free_dma(unsigned int chan, dma_t *dma)
 145 {
 146         struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
 147
 148         free_irq(idma->irq, idma);
 149 }
 150
 151 static void iomd_enable_dma(unsigned int chan, dma_t *dma)
 152 {
 153         struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
 154         unsigned long dma_base = idma->base;
 155         unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
 156
 157         if (idma->dma.invalid) {
 158                 idma->dma.invalid = 0;
 159
 160                 /*
 161                  * Cope with ISA-style drivers which expect cache
 162                  * coherence.
 163                  */
 164                 if (!idma->dma.sg) {
 165                         idma->dma.sg = &idma->dma.buf;
 166                         idma->dma.sgcount = 1;
 167                         idma->dma.buf.length = idma->dma.count;
 168                         idma->dma.buf.dma_address = dma_map_single(NULL,
 169                                 idma->dma.addr, idma->dma.count,
 170                                 idma->dma.dma_mode == DMA_MODE_READ ?
 171                                 DMA_FROM_DEVICE : DMA_TO_DEVICE);
 172                 }
 173
 174                 iomd_writeb(DMA_CR_C, dma_base + CR);
 175                 idma->state = DMA_ST_AB;
 176         }
 177
 178         if (idma->dma.dma_mode == DMA_MODE_READ)
 179                 ctrl |= DMA_CR_D;
 180
 181         iomd_writeb(ctrl, dma_base + CR);
 182         enable_irq(idma->irq);
 183 }
 184
 185 static void iomd_disable_dma(unsigned int chan, dma_t *dma)
 186 {
 187         struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
 188         unsigned long dma_base = idma->base;
 189         unsigned long flags;
 190
 191         local_irq_save(flags);
 192         if (idma->state != ~DMA_ST_AB)
 193                 disable_irq(idma->irq);
 194         iomd_writeb(0, dma_base + CR);
 195         local_irq_restore(flags);
 196 }
 197
 198 static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle)
 199 {
 200         int tcr, speed;
 201
 202         if (cycle < 188)
 203                 speed = 3;
 204         else if (cycle <= 250)
 205                 speed = 2;
 206         else if (cycle < 438)
 207                 speed = 1;
 208         else
 209                 speed = 0;
 210
 211         tcr = iomd_readb(IOMD_DMATCR);
 212         speed &= 3;
 213
 214         switch (chan) {
 215         case DMA_0:
 216                 tcr = (tcr & ~0x03) | speed;
 217                 break;
 218
 219         case DMA_1:
 220                 tcr = (tcr & ~0x0c) | (speed << 2);
 221                 break;
 222
 223         case DMA_2:
 224                 tcr = (tcr & ~0x30) | (speed << 4);
 225                 break;
 226
 227         case DMA_3:
 228                 tcr = (tcr & ~0xc0) | (speed << 6);
 229                 break;
 230
 231         default:
 232                 break;
 233         }
 234
 235         iomd_writeb(tcr, IOMD_DMATCR);
 236
 237         return speed;
 238 }
 239
 240 static struct dma_ops iomd_dma_ops = {
 241         .type           = "IOMD",
 242         .request        = iomd_request_dma,
 243         .free           = iomd_free_dma,
 244         .enable         = iomd_enable_dma,
 245         .disable        = iomd_disable_dma,
 246         .setspeed       = iomd_set_dma_speed,
 247 };
 248
 249 static struct fiq_handler fh = {
 250         .name   = "floppydma"
 251 };
 252
 253 struct floppy_dma {
 254         struct dma_struct       dma;
 255         unsigned int            fiq;
 256 };
 257
 258 static void floppy_enable_dma(unsigned int chan, dma_t *dma)
 259 {
 260         struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
 261         void *fiqhandler_start;
 262         unsigned int fiqhandler_length;
 263         struct pt_regs regs;
 264
 265         if (fdma->dma.sg)
 266                 BUG();
 267
 268         if (fdma->dma.dma_mode == DMA_MODE_READ) {
 269                 extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
 270                 fiqhandler_start = &floppy_fiqin_start;
 271                 fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
 272         } else {
 273                 extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
 274                 fiqhandler_start = &floppy_fiqout_start;
 275                 fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
 276         }
 277
 278         regs.ARM_r9  = fdma->dma.count;
 279         regs.ARM_r10 = (unsigned long)fdma->dma.addr;
 280         regs.ARM_fp  = (unsigned long)FLOPPYDMA_BASE;
 281
 282         if (claim_fiq(&fh)) {
 283                 printk("floppydma: couldn't claim FIQ.\n");
 284                 return;
 285         }
 286
 287         set_fiq_handler(fiqhandler_start, fiqhandler_length);
 288         set_fiq_regs(&regs);
 289         enable_fiq(fdma->fiq);
 290 }
 291
 292 static void floppy_disable_dma(unsigned int chan, dma_t *dma)
 293 {
 294         struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
 295         disable_fiq(fdma->fiq);
 296         release_fiq(&fh);
 297 }
 298
 299 static int floppy_get_residue(unsigned int chan, dma_t *dma)
 300 {
 301         struct pt_regs regs;
 302         get_fiq_regs(&regs);
 303         return regs.ARM_r9;
 304 }
 305
 306 static struct dma_ops floppy_dma_ops = {
 307         .type           = "FIQDMA",
 308         .enable         = floppy_enable_dma,
 309         .disable        = floppy_disable_dma,
 310         .residue        = floppy_get_residue,
 311 };
 312
 313 /*
 314  * This is virtual DMA - we don't need anything here.
 315  */
 316 static void sound_enable_disable_dma(unsigned int chan, dma_t *dma)
 317 {
 318 }
 319
 320 static struct dma_ops sound_dma_ops = {
 321         .type           = "VIRTUAL",
 322         .enable         = sound_enable_disable_dma,
 323         .disable        = sound_enable_disable_dma,
 324 };
 325
 326 static struct iomd_dma iomd_dma[6];
 327
 328 static struct floppy_dma floppy_dma = {
 329         .dma            = {
 330                 .d_ops  = &floppy_dma_ops,
 331         },
 332         .fiq            = FIQ_FLOPPYDATA,
 333 };
 334
 335 static dma_t sound_dma = {
 336         .d_ops          = &sound_dma_ops,
 337 };
 338
 339 static int __init rpc_dma_init(void)
 340 {
 341         unsigned int i;
 342         int ret;
 343
 344         iomd_writeb(0, IOMD_IO0CR);
 345         iomd_writeb(0, IOMD_IO1CR);
 346         iomd_writeb(0, IOMD_IO2CR);
 347         iomd_writeb(0, IOMD_IO3CR);
 348
 349         iomd_writeb(0xa0, IOMD_DMATCR);
 350
 351         /*
 352          * Setup DMA channels 2,3 to be for podules
 353          * and channels 0,1 for internal devices
 354          */
 355         iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
 356
 357         iomd_dma[DMA_0].base    = IOMD_IO0CURA;
 358         iomd_dma[DMA_0].irq     = IRQ_DMA0;
 359         iomd_dma[DMA_1].base    = IOMD_IO1CURA;
 360         iomd_dma[DMA_1].irq     = IRQ_DMA1;
 361         iomd_dma[DMA_2].base    = IOMD_IO2CURA;
 362         iomd_dma[DMA_2].irq     = IRQ_DMA2;
 363         iomd_dma[DMA_3].base    = IOMD_IO3CURA;
 364         iomd_dma[DMA_3].irq     = IRQ_DMA3;
 365         iomd_dma[DMA_S0].base   = IOMD_SD0CURA;
 366         iomd_dma[DMA_S0].irq    = IRQ_DMAS0;
 367         iomd_dma[DMA_S1].base   = IOMD_SD1CURA;
 368         iomd_dma[DMA_S1].irq    = IRQ_DMAS1;
 369
 370         for (i = DMA_0; i <= DMA_S1; i++) {
 371                 iomd_dma[i].dma.d_ops = &iomd_dma_ops;
 372
 373                 ret = isa_dma_add(i, &iomd_dma[i].dma);
 374                 if (ret)
 375                         printk("IOMDDMA%u: unable to register: %d\n", i, ret);
 376         }
 377
 378         ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma);
 379         if (ret)
 380                 printk("IOMDFLOPPY: unable to register: %d\n", ret);
 381         ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma);
 382         if (ret)
 383                 printk("IOMDSOUND: unable to register: %d\n", ret);
 384         return 0;
 385 }
 386 core_initcall(rpc_dma_init);