1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
3 * Copyright (c) 2003-2005,2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/products/EB2410ITX/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/sysdev.h>
20 #include <linux/serial_core.h>
21 #include <linux/platform_device.h>
22 #include <linux/dm9000.h>
23 #include <linux/ata_platform.h>
24 #include <linux/i2c.h>
27 #include <net/ax88796.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
31 #include <asm/mach/irq.h>
33 #include <mach/bast-map.h>
34 #include <mach/bast-irq.h>
35 #include <mach/bast-cpld.h>
37 #include <mach/hardware.h>
39 #include <asm/mach-types.h>
41 //#include <asm/debug-ll.h>
42 #include <plat/regs-serial.h>
43 #include <mach/regs-gpio.h>
44 #include <mach/regs-mem.h>
45 #include <mach/regs-lcd.h>
47 #include <asm/plat-s3c/nand.h>
51 #include <linux/mtd/mtd.h>
52 #include <linux/mtd/nand.h>
53 #include <linux/mtd/nand_ecc.h>
54 #include <linux/mtd/partitions.h>
56 #include <linux/serial_8250.h>
58 #include <plat/clock.h>
59 #include <plat/devs.h>
62 #include "usb-simtec.h"
63 #include "nor-simtec.h"
65 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
67 /* macros for virtual address mods for the io space entries */
68 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
69 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
70 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
71 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
73 /* macros to modify the physical addresses for io space */
75 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
76 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
77 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
78 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
80 static struct map_desc bast_iodesc[] __initdata = {
83 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
84 .pfn = PA_CS2(BAST_PA_ISAIO),
88 .virtual = (u32)S3C24XX_VA_ISA_WORD,
89 .pfn = PA_CS3(BAST_PA_ISAIO),
93 /* bast CPLD control registers, and external interrupt controls */
95 .virtual = (u32)BAST_VA_CTRL1,
96 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
100 .virtual = (u32)BAST_VA_CTRL2,
101 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
105 .virtual = (u32)BAST_VA_CTRL3,
106 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
110 .virtual = (u32)BAST_VA_CTRL4,
111 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
117 .virtual = (u32)BAST_VA_PC104_IRQREQ,
118 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
122 .virtual = (u32)BAST_VA_PC104_IRQRAW,
123 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
127 .virtual = (u32)BAST_VA_PC104_IRQMASK,
128 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
133 /* peripheral space... one for each of fast/slow/byte/16bit */
134 /* note, ide is only decoded in word space, even though some registers
138 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
139 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
140 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
143 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
144 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
145 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
148 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
149 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
150 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
153 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
154 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
155 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
158 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
159 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
160 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
162 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
178 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
185 .clocks = bast_serial_clocks,
186 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
194 .clocks = bast_serial_clocks,
195 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
197 /* port 2 is not actually used */
204 .clocks = bast_serial_clocks,
205 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
209 /* NAND Flash on BAST board */
212 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
214 /* ensure that an nRESET is not generated on resume. */
215 s3c2410_gpio_setpin(S3C2410_GPA21, 1);
216 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
221 static int bast_pm_resume(struct sys_device *sd)
223 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
228 #define bast_pm_suspend NULL
229 #define bast_pm_resume NULL
232 static struct sysdev_class bast_pm_sysclass = {
234 .suspend = bast_pm_suspend,
235 .resume = bast_pm_resume,
238 static struct sys_device bast_pm_sysdev = {
239 .cls = &bast_pm_sysclass,
242 static int smartmedia_map[] = { 0 };
243 static int chip0_map[] = { 1 };
244 static int chip1_map[] = { 2 };
245 static int chip2_map[] = { 3 };
247 static struct mtd_partition bast_default_nand_part[] = {
249 .name = "Boot Agent",
255 .size = SZ_4M - SZ_16K,
261 .size = MTDPART_SIZ_FULL,
265 /* the bast has 4 selectable slots for nand-flash, the three
266 * on-board chip areas, as well as the external SmartMedia
269 * Note, there is no current hot-plug support for the SmartMedia
273 static struct s3c2410_nand_set bast_nand_sets[] = {
275 .name = "SmartMedia",
277 .nr_map = smartmedia_map,
278 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
279 .partitions = bast_default_nand_part,
285 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
286 .partitions = bast_default_nand_part,
292 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
293 .partitions = bast_default_nand_part,
299 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
300 .partitions = bast_default_nand_part,
304 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
308 slot = set->nr_map[slot] & 3;
310 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
311 slot, set, set->nr_map);
313 tmp = __raw_readb(BAST_VA_CTRL2);
314 tmp &= BAST_CPLD_CTLR2_IDERST;
316 tmp |= BAST_CPLD_CTRL2_WNAND;
318 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
320 __raw_writeb(tmp, BAST_VA_CTRL2);
323 static struct s3c2410_platform_nand bast_nand_info = {
327 .nr_sets = ARRAY_SIZE(bast_nand_sets),
328 .sets = bast_nand_sets,
329 .select_chip = bast_nand_select,
334 static struct resource bast_dm9k_resource[] = {
336 .start = S3C2410_CS5 + BAST_PA_DM9000,
337 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
338 .flags = IORESOURCE_MEM,
341 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
342 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
343 .flags = IORESOURCE_MEM,
348 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
353 /* for the moment we limit ourselves to 16bit IO until some
354 * better IO routines can be written and tested
357 static struct dm9000_plat_data bast_dm9k_platdata = {
358 .flags = DM9000_PLATF_16BITONLY,
361 static struct platform_device bast_device_dm9k = {
364 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
365 .resource = bast_dm9k_resource,
367 .platform_data = &bast_dm9k_platdata,
373 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
374 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
375 #define SERIAL_CLK (1843200)
377 static struct plat_serial8250_port bast_sio_data[] = {
379 .mapbase = SERIAL_BASE + 0x2f8,
380 .irq = IRQ_PCSERIAL1,
381 .flags = SERIAL_FLAGS,
384 .uartclk = SERIAL_CLK,
387 .mapbase = SERIAL_BASE + 0x3f8,
388 .irq = IRQ_PCSERIAL2,
389 .flags = SERIAL_FLAGS,
392 .uartclk = SERIAL_CLK,
397 static struct platform_device bast_sio = {
398 .name = "serial8250",
399 .id = PLAT8250_DEV_PLATFORM,
401 .platform_data = &bast_sio_data,
405 /* we have devices on the bus which cannot work much over the
406 * standard 100KHz i2c bus frequency
409 static struct s3c2410_platform_i2c bast_i2c_info = {
412 .bus_freq = 100*1000,
413 .max_freq = 130*1000,
416 /* Asix AX88796 10/100 ethernet controller */
418 static struct ax_plat_data bast_asix_platdata = {
419 .flags = AXFLG_MAC_FROMDEV,
425 static struct resource bast_asix_resource[] = {
427 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
428 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
429 .flags = IORESOURCE_MEM,
432 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
433 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
434 .flags = IORESOURCE_MEM,
439 .flags = IORESOURCE_IRQ
443 static struct platform_device bast_device_asix = {
446 .num_resources = ARRAY_SIZE(bast_asix_resource),
447 .resource = bast_asix_resource,
449 .platform_data = &bast_asix_platdata
453 /* Asix AX88796 10/100 ethernet controller parallel port */
455 static struct resource bast_asixpp_resource[] = {
457 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
458 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
459 .flags = IORESOURCE_MEM,
463 static struct platform_device bast_device_axpp = {
464 .name = "ax88796-pp",
466 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
467 .resource = bast_asixpp_resource,
470 /* LCD/VGA controller */
472 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
474 .type = S3C2410_LCDCON1_TFT,
489 .lcdcon5 = 0x00014b02,
492 .type = S3C2410_LCDCON1_TFT,
507 .lcdcon5 = 0x00014b02,
510 .type = S3C2410_LCDCON1_TFT,
525 .lcdcon5 = 0x00014b02,
529 /* LCD/VGA controller */
531 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
533 .displays = bast_lcd_info,
534 .num_displays = ARRAY_SIZE(bast_lcd_info),
535 .default_display = 1,
538 /* I2C devices fitted. */
540 static struct i2c_board_info bast_i2c_devs[] __initdata = {
542 I2C_BOARD_INFO("tlv320aic23", 0x1a),
544 I2C_BOARD_INFO("simtec-pmu", 0x6b),
546 I2C_BOARD_INFO("ch7013", 0x75),
550 /* Standard BAST devices */
552 static struct platform_device *bast_devices[] __initdata = {
565 static struct clk *bast_clocks[] __initdata = {
573 static void __init bast_map_io(void)
575 /* initialise the clocks */
577 s3c24xx_dclk0.parent = &clk_upll;
578 s3c24xx_dclk0.rate = 12*1000*1000;
580 s3c24xx_dclk1.parent = &clk_upll;
581 s3c24xx_dclk1.rate = 24*1000*1000;
583 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
584 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
586 s3c24xx_uclk.parent = &s3c24xx_clkout1;
588 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
590 s3c_device_nand.dev.platform_data = &bast_nand_info;
591 s3c_device_i2c.dev.platform_data = &bast_i2c_info;
593 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
594 s3c24xx_init_clocks(0);
595 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
600 static void __init bast_init(void)
602 sysdev_class_register(&bast_pm_sysclass);
603 sysdev_register(&bast_pm_sysdev);
605 s3c24xx_fb_set_platdata(&bast_fb_info);
606 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
608 i2c_register_board_info(0, bast_i2c_devs,
609 ARRAY_SIZE(bast_i2c_devs));
614 MACHINE_START(BAST, "Simtec-BAST")
615 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
616 .phys_io = S3C2410_PA_UART,
617 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
618 .boot_params = S3C2410_SDRAM_PA + 0x100,
619 .map_io = bast_map_io,
620 .init_irq = s3c24xx_init_irq,
621 .init_machine = bast_init,
622 .timer = &s3c24xx_timer,