1 /* linux/arch/arm/mach-s3c2412/clock.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2412,S3C2413 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/sysdev.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33 #include <linux/serial_core.h>
36 #include <asm/mach/map.h>
38 #include <mach/hardware.h>
40 #include <plat/regs-serial.h>
41 #include <mach/regs-clock.h>
42 #include <mach/regs-gpio.h>
44 #include <plat/s3c2412.h>
45 #include <plat/clock.h>
48 /* We currently have to assume that the system is running
49 * from the XTPll input, and that all ***REFCLKs are being
50 * fed from it, as we cannot read the state of OM[4] from
53 * It would be possible for each board initialisation to
54 * set the correct muxing at initialisation
57 static int s3c2412_clkcon_enable(struct clk *clk, int enable)
59 unsigned int clocks = clk->ctrlbit;
62 clkcon = __raw_readl(S3C2410_CLKCON);
69 __raw_writel(clkcon, S3C2410_CLKCON);
74 static int s3c2412_upll_enable(struct clk *clk, int enable)
76 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
77 unsigned long orig = upllcon;
80 upllcon |= S3C2412_PLLCON_OFF;
82 upllcon &= ~S3C2412_PLLCON_OFF;
84 __raw_writel(upllcon, S3C2410_UPLLCON);
86 /* allow ~150uS for the PLL to settle and lock */
88 if (enable && (orig & S3C2412_PLLCON_OFF))
94 /* clock selections */
96 static struct clk clk_erefclk = {
101 static struct clk clk_urefclk = {
106 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
108 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
110 if (parent == &clk_urefclk)
111 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
112 else if (parent == &clk_upll)
113 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
117 clk->parent = parent;
119 __raw_writel(clksrc, S3C2412_CLKSRC);
123 static struct clk clk_usysclk = {
127 .ops = &(struct clk_ops) {
128 .set_parent = s3c2412_setparent_usysclk,
132 static struct clk clk_mrefclk = {
138 static struct clk clk_mdivclk = {
144 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
146 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
148 if (parent == &clk_usysclk)
149 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
150 else if (parent == &clk_h)
151 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
155 clk->parent = parent;
157 __raw_writel(clksrc, S3C2412_CLKSRC);
161 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
164 unsigned long parent_rate = clk_get_rate(clk->parent);
167 if (rate > parent_rate)
170 div = parent_rate / rate;
174 return parent_rate / div;
177 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
179 unsigned long parent_rate = clk_get_rate(clk->parent);
180 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
182 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
185 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
187 unsigned long parent_rate = clk_get_rate(clk->parent);
188 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
190 rate = s3c2412_roundrate_usbsrc(clk, rate);
192 if ((parent_rate / rate) == 2)
193 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
195 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
197 __raw_writel(clkdivn, S3C2410_CLKDIVN);
201 static struct clk clk_usbsrc = {
204 .ops = &(struct clk_ops) {
205 .get_rate = s3c2412_getrate_usbsrc,
206 .set_rate = s3c2412_setrate_usbsrc,
207 .round_rate = s3c2412_roundrate_usbsrc,
208 .set_parent = s3c2412_setparent_usbsrc,
212 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
214 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
216 if (parent == &clk_mdivclk)
217 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
218 else if (parent == &clk_mpll)
219 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
223 clk->parent = parent;
225 __raw_writel(clksrc, S3C2412_CLKSRC);
229 static struct clk clk_msysclk = {
232 .ops = &(struct clk_ops) {
233 .set_parent = s3c2412_setparent_msysclk,
237 static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
240 unsigned long clkdiv;
243 /* Note, we current equate fclk andf msysclk for S3C2412 */
245 if (parent == &clk_msysclk || parent == &clk_f)
247 else if (parent == &clk_h)
248 dvs = S3C2412_CLKDIVN_DVSEN;
252 clk->parent = parent;
254 /* update this under irq lockdown, clkdivn is not protected
255 * by the clock system. */
257 local_irq_save(flags);
259 clkdiv = __raw_readl(S3C2410_CLKDIVN);
260 clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
262 __raw_writel(clkdiv, S3C2410_CLKDIVN);
264 local_irq_restore(flags);
269 static struct clk clk_armclk = {
272 .parent = &clk_msysclk,
273 .ops = &(struct clk_ops) {
274 .set_parent = s3c2412_setparent_armclk,
278 /* these next clocks have an divider immediately after them,
279 * so we can register them with their divider and leave out the
280 * intermediate clock stage
282 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
285 unsigned long parent_rate = clk_get_rate(clk->parent);
288 if (rate > parent_rate)
291 /* note, we remove the +/- 1 calculations as they cancel out */
293 div = (rate / parent_rate);
300 return parent_rate / div;
303 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
305 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
307 if (parent == &clk_erefclk)
308 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
309 else if (parent == &clk_mpll)
310 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
314 clk->parent = parent;
316 __raw_writel(clksrc, S3C2412_CLKSRC);
320 static unsigned long s3c2412_getrate_uart(struct clk *clk)
322 unsigned long parent_rate = clk_get_rate(clk->parent);
323 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
325 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
326 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
328 return parent_rate / (div + 1);
331 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
333 unsigned long parent_rate = clk_get_rate(clk->parent);
334 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
336 rate = s3c2412_roundrate_clksrc(clk, rate);
338 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
339 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
341 __raw_writel(clkdivn, S3C2410_CLKDIVN);
345 static struct clk clk_uart = {
348 .ops = &(struct clk_ops) {
349 .get_rate = s3c2412_getrate_uart,
350 .set_rate = s3c2412_setrate_uart,
351 .set_parent = s3c2412_setparent_uart,
352 .round_rate = s3c2412_roundrate_clksrc,
356 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
358 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
360 if (parent == &clk_erefclk)
361 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
362 else if (parent == &clk_mpll)
363 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
367 clk->parent = parent;
369 __raw_writel(clksrc, S3C2412_CLKSRC);
373 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
375 unsigned long parent_rate = clk_get_rate(clk->parent);
376 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
378 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
379 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
381 return parent_rate / (div + 1);
384 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
386 unsigned long parent_rate = clk_get_rate(clk->parent);
387 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
389 rate = s3c2412_roundrate_clksrc(clk, rate);
391 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
392 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
394 __raw_writel(clkdivn, S3C2410_CLKDIVN);
398 static struct clk clk_i2s = {
401 .ops = &(struct clk_ops) {
402 .get_rate = s3c2412_getrate_i2s,
403 .set_rate = s3c2412_setrate_i2s,
404 .set_parent = s3c2412_setparent_i2s,
405 .round_rate = s3c2412_roundrate_clksrc,
409 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
411 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
413 if (parent == &clk_usysclk)
414 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
415 else if (parent == &clk_h)
416 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
420 clk->parent = parent;
422 __raw_writel(clksrc, S3C2412_CLKSRC);
425 static unsigned long s3c2412_getrate_cam(struct clk *clk)
427 unsigned long parent_rate = clk_get_rate(clk->parent);
428 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
430 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
431 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
433 return parent_rate / (div + 1);
436 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
438 unsigned long parent_rate = clk_get_rate(clk->parent);
439 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
441 rate = s3c2412_roundrate_clksrc(clk, rate);
443 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
444 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
446 __raw_writel(clkdivn, S3C2410_CLKDIVN);
450 static struct clk clk_cam = {
451 .name = "camif-upll", /* same as 2440 name */
453 .ops = &(struct clk_ops) {
454 .get_rate = s3c2412_getrate_cam,
455 .set_rate = s3c2412_setrate_cam,
456 .set_parent = s3c2412_setparent_cam,
457 .round_rate = s3c2412_roundrate_clksrc,
461 /* standard clock definitions */
463 static struct clk init_clocks_disable[] = {
468 .enable = s3c2412_clkcon_enable,
469 .ctrlbit = S3C2412_CLKCON_NAND,
474 .enable = s3c2412_clkcon_enable,
475 .ctrlbit = S3C2412_CLKCON_SDI,
480 .enable = s3c2412_clkcon_enable,
481 .ctrlbit = S3C2412_CLKCON_ADC,
486 .enable = s3c2412_clkcon_enable,
487 .ctrlbit = S3C2412_CLKCON_IIC,
492 .enable = s3c2412_clkcon_enable,
493 .ctrlbit = S3C2412_CLKCON_IIS,
498 .enable = s3c2412_clkcon_enable,
499 .ctrlbit = S3C2412_CLKCON_SPI,
503 static struct clk init_clocks[] = {
508 .enable = s3c2412_clkcon_enable,
509 .ctrlbit = S3C2412_CLKCON_DMA0,
514 .enable = s3c2412_clkcon_enable,
515 .ctrlbit = S3C2412_CLKCON_DMA1,
520 .enable = s3c2412_clkcon_enable,
521 .ctrlbit = S3C2412_CLKCON_DMA2,
526 .enable = s3c2412_clkcon_enable,
527 .ctrlbit = S3C2412_CLKCON_DMA3,
532 .enable = s3c2412_clkcon_enable,
533 .ctrlbit = S3C2412_CLKCON_LCDC,
538 .enable = s3c2412_clkcon_enable,
539 .ctrlbit = S3C2412_CLKCON_GPIO,
544 .enable = s3c2412_clkcon_enable,
545 .ctrlbit = S3C2412_CLKCON_USBH,
547 .name = "usb-device",
550 .enable = s3c2412_clkcon_enable,
551 .ctrlbit = S3C2412_CLKCON_USBD,
556 .enable = s3c2412_clkcon_enable,
557 .ctrlbit = S3C2412_CLKCON_PWMT,
562 .enable = s3c2412_clkcon_enable,
563 .ctrlbit = S3C2412_CLKCON_UART0,
568 .enable = s3c2412_clkcon_enable,
569 .ctrlbit = S3C2412_CLKCON_UART1,
574 .enable = s3c2412_clkcon_enable,
575 .ctrlbit = S3C2412_CLKCON_UART2,
580 .enable = s3c2412_clkcon_enable,
581 .ctrlbit = S3C2412_CLKCON_RTC,
588 .name = "usb-bus-gadget",
590 .parent = &clk_usb_bus,
591 .enable = s3c2412_clkcon_enable,
592 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
594 .name = "usb-bus-host",
596 .parent = &clk_usb_bus,
597 .enable = s3c2412_clkcon_enable,
598 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
602 /* clocks to add where we need to check their parentage */
611 static struct clk_init clks_src[] __initdata = {
614 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
615 .src_0 = &clk_urefclk,
619 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
620 .src_0 = &clk_erefclk,
624 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
625 .src_0 = &clk_usysclk,
629 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
630 .src_0 = &clk_mdivclk,
634 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
635 .src_0 = &clk_erefclk,
639 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
640 .src_0 = &clk_usysclk,
642 /* here we assume OM[4] select xtal */
645 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
650 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
656 /* s3c2412_clk_initparents
658 * Initialise the parents for the clocks that we get at start-time
661 static void __init s3c2412_clk_initparents(void)
663 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
664 struct clk_init *cip = clks_src;
669 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
670 ret = s3c24xx_register_clock(cip->clk);
672 printk(KERN_ERR "Failed to register clock %s (%d)\n",
673 cip->clk->name, ret);
676 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
678 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
679 clk_set_parent(cip->clk, src);
683 /* clocks to add straight away */
685 static struct clk *clks[] __initdata = {
692 int __init s3c2412_baseclk_add(void)
694 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
700 clk_upll.enable = s3c2412_upll_enable;
701 clk_usb_bus.parent = &clk_usbsrc;
702 clk_usb_bus.rate = 0x0;
704 clk_f.parent = &clk_msysclk;
706 s3c2412_clk_initparents();
708 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
711 ret = s3c24xx_register_clock(clkp);
713 printk(KERN_ERR "Failed to register clock %s (%d)\n",
718 /* set the dvs state according to what we got at boot time */
720 dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
723 clk_armclk.parent = &clk_h;
725 printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
727 /* ensure usb bus clock is within correct rate of 48MHz */
729 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
730 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
732 /* for the moment, let's use the UPLL, and see if we can
735 clk_set_parent(&clk_usysclk, &clk_upll);
736 clk_set_parent(&clk_usbsrc, &clk_usysclk);
737 clk_set_rate(&clk_usbsrc, 48*1000*1000);
740 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
741 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
742 print_mhz(clk_get_rate(&clk_upll)),
743 print_mhz(clk_get_rate(&clk_usb_bus)));
745 /* register clocks from clock array */
748 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
749 /* ensure that we note the clock state */
751 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
753 ret = s3c24xx_register_clock(clkp);
755 printk(KERN_ERR "Failed to register clock %s (%d)\n",
760 /* We must be careful disabling the clocks we are not intending to
761 * be using at boot time, as subsystems such as the LCD which do
762 * their own DMA requests to the bus can cause the system to lockup
763 * if they where in the middle of requesting bus access.
765 * Disabling the LCD clock if the LCD is active is very dangerous,
766 * and therefore the bootloader should be careful to not enable
767 * the LCD clock if it is not needed.
770 /* install (and disable) the clocks we do not need immediately */
772 clkp = init_clocks_disable;
773 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
775 ret = s3c24xx_register_clock(clkp);
777 printk(KERN_ERR "Failed to register clock %s (%d)\n",
781 s3c2412_clkcon_enable(clkp, 0);