1 /* linux/arch/arm/mach-s3c2416/clock.c
3 * Copyright (c) 2010 Simtec Electronics
4 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
6 * S3C2416 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/clk.h>
17 #include <plat/s3c2416.h>
18 #include <plat/s3c2443.h>
19 #include <plat/clock.h>
20 #include <plat/clock-clksrc.h>
23 #include <plat/cpu-freq.h>
26 #include <asm/mach/map.h>
28 #include <mach/regs-clock.h>
29 #include <mach/regs-s3c2443-clock.h>
33 * this clock is sourced from msysclk and can have a number of
34 * divider values applied to it to then be fed into armclk.
35 * The real clock definition is done in s3c2443-clock.c,
36 * only the armdiv divisor table must be defined here.
39 static unsigned int armdiv[8] = {
48 static struct clksrc_clk hsspi_eplldiv = {
50 .name = "hsspi-eplldiv",
51 .parent = &clk_esysclk.clk,
53 .enable = s3c2443_clkcon_enable_s,
55 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
58 static struct clk *hsspi_sources[] = {
59 [0] = &hsspi_eplldiv.clk,
60 [1] = NULL, /* to fix */
63 static struct clksrc_clk hsspi_mux = {
67 .sources = &(struct clksrc_sources) {
68 .sources = hsspi_sources,
69 .nr_sources = ARRAY_SIZE(hsspi_sources),
71 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
74 static struct clksrc_clk hsmmc_div[] = {
78 .devname = "s3c-sdhci.0",
79 .parent = &clk_esysclk.clk,
81 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
86 .devname = "s3c-sdhci.1",
87 .parent = &clk_esysclk.clk,
89 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
93 static struct clksrc_clk hsmmc_mux[] = {
97 .devname = "s3c-sdhci.0",
99 .enable = s3c2443_clkcon_enable_s,
101 .sources = &(struct clksrc_sources) {
103 .sources = (struct clk *[]) {
104 [0] = &hsmmc_div[0].clk,
105 [1] = NULL, /* to fix */
108 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
113 .devname = "s3c-sdhci.1",
114 .ctrlbit = (1 << 12),
115 .enable = s3c2443_clkcon_enable_s,
117 .sources = &(struct clksrc_sources) {
119 .sources = (struct clk *[]) {
120 [0] = &hsmmc_div[1].clk,
121 [1] = NULL, /* to fix */
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
128 static struct clk hsmmc0_clk = {
130 .devname = "s3c-sdhci.0",
132 .enable = s3c2443_clkcon_enable_h,
133 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
136 void __init_or_cpufreq s3c2416_setup_clocks(void)
138 s3c2443_common_setup_clocks(s3c2416_get_pll);
142 static struct clksrc_clk *clksrcs[] __initdata = {
151 void __init s3c2416_init_clocks(int xtal)
153 u32 epllcon = __raw_readl(S3C2443_EPLLCON);
154 u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
157 /* s3c2416 EPLL compatible with s3c64xx */
158 clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
160 clk_epll.parent = &clk_epllref.clk;
162 s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
163 armdiv, ARRAY_SIZE(armdiv),
164 S3C2416_CLKDIV0_ARMDIV_MASK);
166 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
167 s3c_register_clksrc(clksrcs[ptr], 1);
169 s3c24xx_register_clock(&hsmmc0_clk);