1 /* linux/arch/arm/mach-s3c2440/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2440 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
23 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-ac97.h>
29 #include <plat/regs-dma.h>
30 #include <mach/regs-mem.h>
31 #include <mach/regs-lcd.h>
32 #include <mach/regs-sdi.h>
33 #include <plat/regs-iis.h>
34 #include <plat/regs-spi.h>
36 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
39 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
43 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
54 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
58 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
62 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
66 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
70 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
74 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
75 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
76 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
80 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
81 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
85 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
86 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
90 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
91 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
95 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
96 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
100 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
101 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
105 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
109 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
113 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
117 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
121 static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
122 struct s3c24xx_dma_map *map)
124 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
127 static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
128 .select = s3c2440_dma_select,
129 .dcon_mask = 7 << 24,
130 .map = s3c2440_dma_mappings,
131 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
134 static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
138 [0] = 3 | DMA_CH_VALID,
139 [1] = 2 | DMA_CH_VALID,
140 [2] = 1 | DMA_CH_VALID,
141 [3] = 0 | DMA_CH_VALID,
146 [0] = 1 | DMA_CH_VALID,
147 [1] = 2 | DMA_CH_VALID,
152 [0] = 2 | DMA_CH_VALID,
153 [1] = 1 | DMA_CH_VALID,
158 [0] = 2 | DMA_CH_VALID,
159 [1] = 1 | DMA_CH_VALID,
164 [0] = 1 | DMA_CH_VALID,
165 [1] = 3 | DMA_CH_VALID,
170 [0] = 3 | DMA_CH_VALID,
171 [1] = 2 | DMA_CH_VALID,
177 static int __init s3c2440_dma_add(struct device *dev)
180 s3c24xx_dma_order_set(&s3c2440_dma_order);
181 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
184 static struct subsys_interface s3c2440_dma_interface = {
185 .name = "s3c2440_dma",
186 .subsys = &s3c2440_subsys,
187 .add_dev = s3c2440_dma_add,
190 static int __init s3c2440_dma_init(void)
192 return subsys_interface_register(&s3c2440_dma_interface);
195 arch_initcall(s3c2440_dma_init);