arch/arm/mach-s3c2440/mach-rx3715.c

   1 /* linux/arch/arm/mach-s3c2440/mach-rx3715.c
   2  *
   3  * Copyright (c) 2003-2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.handhelds.org/projects/rx3715.html
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/list.h>
  18 #include <linux/memblock.h>
  19 #include <linux/timer.h>
  20 #include <linux/init.h>
  21 #include <linux/tty.h>
  22 #include <linux/console.h>
  23 #include <linux/device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/serial.h>
  27 #include <linux/io.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/nand.h>
  30 #include <linux/mtd/nand_ecc.h>
  31 #include <linux/mtd/partitions.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/mach/irq.h>
  36
  37 #include <mach/hardware.h>
  38 #include <asm/irq.h>
  39 #include <asm/mach-types.h>
  40
  41 #include <plat/regs-serial.h>
  42 #include <mach/regs-gpio.h>
  43 #include <mach/regs-lcd.h>
  44
  45 #include <mach/h1940.h>
  46 #include <plat/nand.h>
  47 #include <mach/fb.h>
  48
  49 #include <plat/clock.h>
  50 #include <plat/devs.h>
  51 #include <plat/cpu.h>
  52 #include <plat/pm.h>
  53
  54 #include "common.h"
  55
  56 static struct map_desc rx3715_iodesc[] __initdata = {
  57         /* dump ISA space somewhere unused */
  58
  59         {
  60                 .virtual        = (u32)S3C24XX_VA_ISA_WORD,
  61                 .pfn            = __phys_to_pfn(S3C2410_CS3),
  62                 .length         = SZ_1M,
  63                 .type           = MT_DEVICE,
  64         }, {
  65                 .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
  66                 .pfn            = __phys_to_pfn(S3C2410_CS3),
  67                 .length         = SZ_1M,
  68                 .type           = MT_DEVICE,
  69         },
  70 };
  71
  72
  73 static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
  74         [0] = {
  75                 .name           = "fclk",
  76                 .divisor        = 0,
  77                 .min_baud       = 0,
  78                 .max_baud       = 0,
  79         }
  80 };
  81
  82 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
  83         [0] = {
  84                 .hwport      = 0,
  85                 .flags       = 0,
  86                 .ucon        = 0x3c5,
  87                 .ulcon       = 0x03,
  88                 .ufcon       = 0x51,
  89                 .clocks      = rx3715_serial_clocks,
  90                 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
  91         },
  92         [1] = {
  93                 .hwport      = 1,
  94                 .flags       = 0,
  95                 .ucon        = 0x3c5,
  96                 .ulcon       = 0x03,
  97                 .ufcon       = 0x00,
  98                 .clocks      = rx3715_serial_clocks,
  99                 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
 100         },
 101         /* IR port */
 102         [2] = {
 103                 .hwport      = 2,
 104                 .uart_flags  = UPF_CONS_FLOW,
 105                 .ucon        = 0x3c5,
 106                 .ulcon       = 0x43,
 107                 .ufcon       = 0x51,
 108                 .clocks      = rx3715_serial_clocks,
 109                 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
 110         }
 111 };
 112
 113 /* framebuffer lcd controller information */
 114
 115 static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
 116         .lcdcon5 =      S3C2410_LCDCON5_INVVLINE |
 117                         S3C2410_LCDCON5_FRM565 |
 118                         S3C2410_LCDCON5_HWSWP,
 119
 120         .type           = S3C2410_LCDCON1_TFT,
 121         .width          = 240,
 122         .height         = 320,
 123
 124         .pixclock       = 260000,
 125         .xres           = 240,
 126         .yres           = 320,
 127         .bpp            = 16,
 128         .left_margin    = 36,
 129         .right_margin   = 36,
 130         .hsync_len      = 8,
 131         .upper_margin   = 6,
 132         .lower_margin   = 7,
 133         .vsync_len      = 3,
 134 };
 135
 136 static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
 137
 138         .displays =     &rx3715_lcdcfg,
 139         .num_displays = 1,
 140         .default_display = 0,
 141
 142         .lpcsel =       0xf82,
 143
 144         .gpccon =       0xaa955699,
 145         .gpccon_mask =  0xffc003cc,
 146         .gpcup =        0x0000ffff,
 147         .gpcup_mask =   0xffffffff,
 148
 149         .gpdcon =       0xaa95aaa1,
 150         .gpdcon_mask =  0xffc0fff0,
 151         .gpdup =        0x0000faff,
 152         .gpdup_mask =   0xffffffff,
 153 };
 154
 155 static struct mtd_partition __initdata rx3715_nand_part[] = {
 156         [0] = {
 157                 .name           = "Whole Flash",
 158                 .offset         = 0,
 159                 .size           = MTDPART_SIZ_FULL,
 160                 .mask_flags     = MTD_WRITEABLE,
 161         }
 162 };
 163
 164 static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
 165         [0] = {
 166                 .name           = "Internal",
 167                 .nr_chips       = 1,
 168                 .nr_partitions  = ARRAY_SIZE(rx3715_nand_part),
 169                 .partitions     = rx3715_nand_part,
 170         },
 171 };
 172
 173 static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
 174         .tacls          = 25,
 175         .twrph0         = 50,
 176         .twrph1         = 15,
 177         .nr_sets        = ARRAY_SIZE(rx3715_nand_sets),
 178         .sets           = rx3715_nand_sets,
 179 };
 180
 181 static struct platform_device *rx3715_devices[] __initdata = {
 182         &s3c_device_ohci,
 183         &s3c_device_lcd,
 184         &s3c_device_wdt,
 185         &s3c_device_i2c0,
 186         &s3c_device_iis,
 187         &s3c_device_nand,
 188 };
 189
 190 static void __init rx3715_map_io(void)
 191 {
 192         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
 193         s3c24xx_init_clocks(16934000);
 194         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
 195 }
 196
 197 /* H1940 and RX3715 need to reserve this for suspend */
 198 static void __init rx3715_reserve(void)
 199 {
 200         memblock_reserve(0x30003000, 0x1000);
 201         memblock_reserve(0x30081000, 0x1000);
 202 }
 203
 204 static void __init rx3715_init_irq(void)
 205 {
 206         s3c24xx_init_irq();
 207 }
 208
 209 static void __init rx3715_init_machine(void)
 210 {
 211 #ifdef CONFIG_PM_H1940
 212         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
 213 #endif
 214         s3c_pm_init();
 215
 216         s3c_nand_set_platdata(&rx3715_nand_info);
 217         s3c24xx_fb_set_platdata(&rx3715_fb_info);
 218         platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
 219 }
 220
 221 MACHINE_START(RX3715, "IPAQ-RX3715")
 222         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
 223         .atag_offset    = 0x100,
 224         .map_io         = rx3715_map_io,
 225         .reserve        = rx3715_reserve,
 226         .init_irq       = rx3715_init_irq,
 227         .init_machine   = rx3715_init_machine,
 228         .timer          = &s3c24xx_timer,
 229         .restart        = s3c2440_restart,
 230 MACHINE_END