1 /* linux/arch/arm/mach-s3c2443/clock.c
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2443 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/errno.h>
29 #include <linux/err.h>
30 #include <linux/sysdev.h>
31 #include <linux/clk.h>
32 #include <linux/mutex.h>
33 #include <linux/serial_core.h>
36 #include <asm/mach/map.h>
38 #include <mach/hardware.h>
40 #include <mach/regs-s3c2443-clock.h>
42 #include <plat/cpu-freq.h>
44 #include <plat/s3c2443.h>
45 #include <plat/clock.h>
46 #include <plat/clock-clksrc.h>
49 /* We currently have to assume that the system is running
50 * from the XTPll input, and that all ***REFCLKs are being
51 * fed from it, as we cannot read the state of OM[4] from
54 * It would be possible for each board initialisation to
55 * set the correct muxing at initialisation
58 /* clock selections */
60 static struct clk clk_i2s_ext = {
67 * this clock is sourced from msysclk and can have a number of
68 * divider values applied to it to then be fed into armclk.
71 /* armdiv divisor table */
73 static unsigned int armdiv[16] = {
74 [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
75 [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
76 [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
77 [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
78 [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
79 [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
80 [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
81 [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
84 static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
86 clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
88 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
91 static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
94 unsigned long parent = clk_get_rate(clk->parent);
96 unsigned best = 256; /* bigger than any value */
100 for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
103 if (calc <= rate && div < best)
107 return parent / best;
110 static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
112 unsigned long parent = clk_get_rate(clk->parent);
115 unsigned best = 256; /* bigger than any value */
119 for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
122 if (calc <= rate && div < best) {
129 unsigned long clkcon0;
131 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
132 clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
133 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
134 __raw_writel(clkcon0, S3C2443_CLKDIV0);
137 return (val == -1) ? -EINVAL : 0;
140 static struct clk clk_armdiv = {
143 .parent = &clk_msysclk.clk,
144 .ops = &(struct clk_ops) {
145 .round_rate = s3c2443_armclk_roundrate,
146 .set_rate = s3c2443_armclk_setrate,
152 * this is the clock fed into the ARM core itself, from armdiv or from hclk.
155 static struct clk *clk_arm_sources[] = {
160 static struct clksrc_clk clk_arm = {
165 .sources = &(struct clksrc_sources) {
166 .sources = clk_arm_sources,
167 .nr_sources = ARRAY_SIZE(clk_arm_sources),
169 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
174 * high-speed spi clock, sourced from esysclk
177 static struct clksrc_clk clk_hsspi = {
181 .parent = &clk_esysclk.clk,
182 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
183 .enable = s3c2443_clkcon_enable_s,
185 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
191 * this clock is sourced from epll, and is fed through a divider,
192 * to a mux controlled by sclkcon where either it or a extclk can
193 * be fed to the hsmmc block
196 static struct clksrc_clk clk_hsmmc_div = {
200 .parent = &clk_esysclk.clk,
202 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
205 static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
207 unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
209 clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
210 S3C2443_SCLKCON_HSMMCCLK_EPLL);
212 if (parent == &clk_epll)
213 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
214 else if (parent == &clk_ext)
215 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
219 if (clk->usage > 0) {
220 __raw_writel(clksrc, S3C2443_SCLKCON);
223 clk->parent = parent;
227 static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
229 return s3c2443_setparent_hsmmc(clk, clk->parent);
232 static struct clk clk_hsmmc = {
235 .parent = &clk_hsmmc_div.clk,
236 .enable = s3c2443_enable_hsmmc,
237 .ops = &(struct clk_ops) {
238 .set_parent = s3c2443_setparent_hsmmc,
244 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
245 * from the mux that comes after it (cannot merge into one single clock)
248 static struct clksrc_clk clk_i2s_eplldiv = {
250 .name = "i2s-eplldiv",
252 .parent = &clk_esysclk.clk,
254 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
259 * i2s bus reference clock, selectable from external, esysclk or epllref
261 * Note, this used to be two clocks, but was compressed into one.
264 struct clk *clk_i2s_srclist[] = {
265 [0] = &clk_i2s_eplldiv.clk,
267 [2] = &clk_epllref.clk,
268 [3] = &clk_epllref.clk,
271 static struct clksrc_clk clk_i2s = {
275 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
276 .enable = s3c2443_clkcon_enable_s,
279 .sources = &(struct clksrc_sources) {
280 .sources = clk_i2s_srclist,
281 .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
283 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
286 /* standard clock definitions */
288 static struct clk init_clocks_off[] = {
293 .enable = s3c2443_clkcon_enable_p,
294 .ctrlbit = S3C2443_PCLKCON_SDI,
299 .enable = s3c2443_clkcon_enable_p,
300 .ctrlbit = S3C2443_PCLKCON_IIS,
305 .enable = s3c2443_clkcon_enable_p,
306 .ctrlbit = S3C2443_PCLKCON_SPI0,
311 .enable = s3c2443_clkcon_enable_p,
312 .ctrlbit = S3C2443_PCLKCON_SPI1,
316 static struct clk init_clocks[] = {
319 /* clocks to add straight away */
321 static struct clksrc_clk *clksrcs[] __initdata = {
329 static struct clk *clks[] __initdata = {
334 void __init_or_cpufreq s3c2443_setup_clocks(void)
336 s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
339 void __init s3c2443_init_clocks(int xtal)
341 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
344 clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
345 clk_epll.parent = &clk_epllref.clk;
347 s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
349 s3c2443_setup_clocks();
351 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
353 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
354 s3c_register_clksrc(clksrcs[ptr], 1);
356 /* register clocks from clock array */
358 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
360 /* We must be careful disabling the clocks we are not intending to
361 * be using at boot time, as subsystems such as the LCD which do
362 * their own DMA requests to the bus can cause the system to lockup
363 * if they where in the middle of requesting bus access.
365 * Disabling the LCD clock if the LCD is active is very dangerous,
366 * and therefore the bootloader should be careful to not enable
367 * the LCD clock if it is not needed.
370 /* install (and disable) the clocks we do not need immediately */
372 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
373 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));