1 /* linux/arch/arm/mach-s3c2410/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
24 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-dma.h>
29 #include <mach/regs-lcd.h>
30 #include <mach/regs-sdi.h>
31 #include <plat/regs-spi.h>
33 static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
36 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
40 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
44 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
45 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
46 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
50 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
54 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
58 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
62 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
66 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
70 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
71 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
72 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
76 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
77 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
81 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
85 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
89 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
93 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
97 .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
101 static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
102 struct s3c24xx_dma_map *map)
104 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
107 static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
108 .select = s3c2410_dma_select,
109 .dcon_mask = 7 << 24,
110 .map = s3c2410_dma_mappings,
111 .map_size = ARRAY_SIZE(s3c2410_dma_mappings),
114 static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
118 [0] = 3 | DMA_CH_VALID,
119 [1] = 2 | DMA_CH_VALID,
120 [2] = 0 | DMA_CH_VALID,
125 [0] = 1 | DMA_CH_VALID,
126 [1] = 2 | DMA_CH_VALID,
132 static int __init s3c2410_dma_add(struct device *dev,
133 struct subsys_interface *sif)
136 s3c24xx_dma_order_set(&s3c2410_dma_order);
137 return s3c24xx_dma_init_map(&s3c2410_dma_sel);
140 #if defined(CONFIG_CPU_S3C2410)
141 static struct subsys_interface s3c2410_dma_interface = {
142 .name = "s3c2410_dma",
143 .subsys = &s3c2410_subsys,
144 .add_dev = s3c2410_dma_add,
147 static int __init s3c2410_dma_drvinit(void)
149 return subsys_interface_register(&s3c2410_dma_interface);
152 arch_initcall(s3c2410_dma_drvinit);
154 static struct subsys_interface s3c2410a_dma_interface = {
155 .name = "s3c2410a_dma",
156 .subsys = &s3c2410a_subsys,
157 .add_dev = s3c2410_dma_add,
160 static int __init s3c2410a_dma_drvinit(void)
162 return subsys_interface_register(&s3c2410a_dma_interface);
165 arch_initcall(s3c2410a_dma_drvinit);
168 #if defined(CONFIG_CPU_S3C2442)
169 /* S3C2442 DMA contains the same selection table as the S3C2410 */
170 static struct subsys_interface s3c2442_dma_interface = {
171 .name = "s3c2442_dma",
172 .subsys = &s3c2442_subsys,
173 .add_dev = s3c2410_dma_add,
176 static int __init s3c2442_dma_drvinit(void)
178 return subsys_interface_register(&s3c2442_dma_interface);
181 arch_initcall(s3c2442_dma_drvinit);