1 /* linux/arch/arm/mach-s3c2412/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2412 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
23 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-dma.h>
29 #include <mach/regs-lcd.h>
30 #include <plat/regs-spi.h>
32 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
34 static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
37 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
38 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0),
42 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
43 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1),
47 .channels = MAP(S3C2412_DMAREQSEL_SDI),
48 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
52 .channels = MAP(S3C2412_DMAREQSEL_SPI0RX),
53 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
57 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
58 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0TX),
62 .channels = MAP(S3C2412_DMAREQSEL_SPI1RX),
63 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
67 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
68 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1TX),
72 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
73 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
77 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
78 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
82 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
83 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
85 [DMACH_UART0_SRC2] = {
87 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
88 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
90 [DMACH_UART1_SRC2] = {
92 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
93 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
95 [DMACH_UART2_SRC2] = {
97 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
98 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
102 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
103 .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER),
107 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
108 .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX),
112 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
113 .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX),
117 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
118 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1),
122 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
123 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2),
127 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
128 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3),
132 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
133 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4),
137 static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
138 struct s3c24xx_dma_map *map,
139 enum dma_data_direction dir)
143 if (dir == DMA_FROM_DEVICE)
144 chsel = map->channels_rx[0];
146 chsel = map->channels[0];
148 chsel &= ~DMA_CH_VALID;
149 chsel |= S3C2412_DMAREQSEL_HW;
151 writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
154 static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
155 struct s3c24xx_dma_map *map)
157 s3c2412_dma_direction(chan, map, chan->source);
160 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
161 .select = s3c2412_dma_select,
162 .direction = s3c2412_dma_direction,
164 .map = s3c2412_dma_mappings,
165 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
168 static int __init s3c2412_dma_add(struct device *dev,
169 struct subsys_interface *sif)
172 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
175 static struct subsys_interface s3c2412_dma_interface = {
176 .name = "s3c2412_dma",
177 .subsys = &s3c2412_subsys,
178 .add_dev = s3c2412_dma_add,
181 static int __init s3c2412_dma_init(void)
183 return subsys_interface_register(&s3c2412_dma_interface);
186 arch_initcall(s3c2412_dma_init);