arch/arm/mach-s3c24xx/dma-s3c2440.c

   1 /* linux/arch/arm/mach-s3c2440/dma.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2440 DMA selection
   7  *
   8  * http://armlinux.simtec.co.uk/
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/serial_core.h>
  19
  20 #include <mach/map.h>
  21 #include <mach/dma.h>
  22
  23 #include <plat/dma-s3c24xx.h>
  24 #include <plat/cpu.h>
  25
  26 #include <plat/regs-serial.h>
  27 #include <mach/regs-gpio.h>
  28 #include <plat/regs-ac97.h>
  29 #include <plat/regs-dma.h>
  30 #include <mach/regs-lcd.h>
  31 #include <mach/regs-sdi.h>
  32 #include <plat/regs-iis.h>
  33 #include <plat/regs-spi.h>
  34
  35 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
  36         [DMACH_XD0] = {
  37                 .name           = "xdreq0",
  38                 .channels[0]    = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  39         },
  40         [DMACH_XD1] = {
  41                 .name           = "xdreq1",
  42                 .channels[1]    = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  43         },
  44         [DMACH_SDI] = {
  45                 .name           = "sdi",
  46                 .channels[0]    = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  47                 .channels[1]    = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
  48                 .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  49                 .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  50         },
  51         [DMACH_SPI0] = {
  52                 .name           = "spi0",
  53                 .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  54         },
  55         [DMACH_SPI1] = {
  56                 .name           = "spi1",
  57                 .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  58         },
  59         [DMACH_UART0] = {
  60                 .name           = "uart0",
  61                 .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  62         },
  63         [DMACH_UART1] = {
  64                 .name           = "uart1",
  65                 .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  66         },
  67         [DMACH_UART2] = {
  68                 .name           = "uart2",
  69                 .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  70         },
  71         [DMACH_TIMER] = {
  72                 .name           = "timer",
  73                 .channels[0]    = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  74                 .channels[2]    = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  75                 .channels[3]    = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  76         },
  77         [DMACH_I2S_IN] = {
  78                 .name           = "i2s-sdi",
  79                 .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  80                 .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  81         },
  82         [DMACH_I2S_OUT] = {
  83                 .name           = "i2s-sdo",
  84                 .channels[0]    = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
  85                 .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  86         },
  87         [DMACH_PCM_IN] = {
  88                 .name           = "pcm-in",
  89                 .channels[0]    = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
  90                 .channels[2]    = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
  91         },
  92         [DMACH_PCM_OUT] = {
  93                 .name           = "pcm-out",
  94                 .channels[1]    = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
  95                 .channels[3]    = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
  96         },
  97         [DMACH_MIC_IN] = {
  98                 .name           = "mic-in",
  99                 .channels[2]    = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
 100                 .channels[3]    = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
 101         },
 102         [DMACH_USB_EP1] = {
 103                 .name           = "usb-ep1",
 104                 .channels[0]    = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
 105         },
 106         [DMACH_USB_EP2] = {
 107                 .name           = "usb-ep2",
 108                 .channels[1]    = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
 109         },
 110         [DMACH_USB_EP3] = {
 111                 .name           = "usb-ep3",
 112                 .channels[2]    = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
 113         },
 114         [DMACH_USB_EP4] = {
 115                 .name           = "usb-ep4",
 116                 .channels[3]    = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
 117         },
 118 };
 119
 120 static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
 121                                struct s3c24xx_dma_map *map)
 122 {
 123         chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
 124 }
 125
 126 static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
 127         .select         = s3c2440_dma_select,
 128         .dcon_mask      = 7 << 24,
 129         .map            = s3c2440_dma_mappings,
 130         .map_size       = ARRAY_SIZE(s3c2440_dma_mappings),
 131 };
 132
 133 static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
 134         .channels       = {
 135                 [DMACH_SDI]     = {
 136                         .list   = {
 137                                 [0]     = 3 | DMA_CH_VALID,
 138                                 [1]     = 2 | DMA_CH_VALID,
 139                                 [2]     = 1 | DMA_CH_VALID,
 140                                 [3]     = 0 | DMA_CH_VALID,
 141                         },
 142                 },
 143                 [DMACH_I2S_IN]  = {
 144                         .list   = {
 145                                 [0]     = 1 | DMA_CH_VALID,
 146                                 [1]     = 2 | DMA_CH_VALID,
 147                         },
 148                 },
 149                 [DMACH_I2S_OUT] = {
 150                         .list   = {
 151                                 [0]     = 2 | DMA_CH_VALID,
 152                                 [1]     = 1 | DMA_CH_VALID,
 153                         },
 154                 },
 155                 [DMACH_PCM_IN] = {
 156                         .list   = {
 157                                 [0]     = 2 | DMA_CH_VALID,
 158                                 [1]     = 1 | DMA_CH_VALID,
 159                         },
 160                 },
 161                 [DMACH_PCM_OUT] = {
 162                         .list   = {
 163                                 [0]     = 1 | DMA_CH_VALID,
 164                                 [1]     = 3 | DMA_CH_VALID,
 165                         },
 166                 },
 167                 [DMACH_MIC_IN] = {
 168                         .list   = {
 169                                 [0]     = 3 | DMA_CH_VALID,
 170                                 [1]     = 2 | DMA_CH_VALID,
 171                         },
 172                 },
 173         },
 174 };
 175
 176 static int __init s3c2440_dma_add(struct device *dev,
 177                                   struct subsys_interface *sif)
 178 {
 179         s3c2410_dma_init();
 180         s3c24xx_dma_order_set(&s3c2440_dma_order);
 181         return s3c24xx_dma_init_map(&s3c2440_dma_sel);
 182 }
 183
 184 static struct subsys_interface s3c2440_dma_interface = {
 185         .name           = "s3c2440_dma",
 186         .subsys         = &s3c2440_subsys,
 187         .add_dev        = s3c2440_dma_add,
 188 };
 189
 190 static int __init s3c2440_dma_init(void)
 191 {
 192         return subsys_interface_register(&s3c2440_dma_interface);
 193 }
 194
 195 arch_initcall(s3c2440_dma_init);
 196