1 /* linux/arch/arm/mach-s3c2440/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2440 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
23 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-dma.h>
29 #include <mach/regs-lcd.h>
30 #include <mach/regs-sdi.h>
31 #include <plat/regs-spi.h>
33 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
36 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
40 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
44 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
45 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
46 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
47 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
51 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
55 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
59 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
63 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
67 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
71 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
72 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
73 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
77 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
78 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
82 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
83 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
87 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
88 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
92 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
93 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
97 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
98 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
102 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
106 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
110 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
114 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
118 static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
119 struct s3c24xx_dma_map *map)
121 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
124 static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
125 .select = s3c2440_dma_select,
126 .dcon_mask = 7 << 24,
127 .map = s3c2440_dma_mappings,
128 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
131 static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
135 [0] = 3 | DMA_CH_VALID,
136 [1] = 2 | DMA_CH_VALID,
137 [2] = 1 | DMA_CH_VALID,
138 [3] = 0 | DMA_CH_VALID,
143 [0] = 1 | DMA_CH_VALID,
144 [1] = 2 | DMA_CH_VALID,
149 [0] = 2 | DMA_CH_VALID,
150 [1] = 1 | DMA_CH_VALID,
155 [0] = 2 | DMA_CH_VALID,
156 [1] = 1 | DMA_CH_VALID,
161 [0] = 1 | DMA_CH_VALID,
162 [1] = 3 | DMA_CH_VALID,
167 [0] = 3 | DMA_CH_VALID,
168 [1] = 2 | DMA_CH_VALID,
174 static int __init s3c2440_dma_add(struct device *dev,
175 struct subsys_interface *sif)
178 s3c24xx_dma_order_set(&s3c2440_dma_order);
179 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
182 static struct subsys_interface s3c2440_dma_interface = {
183 .name = "s3c2440_dma",
184 .subsys = &s3c2440_subsys,
185 .add_dev = s3c2440_dma_add,
188 static int __init s3c2440_dma_init(void)
190 return subsys_interface_register(&s3c2440_dma_interface);
193 arch_initcall(s3c2440_dma_init);