arch/arm/mach-s3c24xx/dma-s3c2440.c

   1 /* linux/arch/arm/mach-s3c2440/dma.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2440 DMA selection
   7  *
   8  * http://armlinux.simtec.co.uk/
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/serial_core.h>
  19
  20 #include <mach/map.h>
  21 #include <mach/dma.h>
  22
  23 #include <plat/dma-s3c24xx.h>
  24 #include <plat/cpu.h>
  25
  26 #include <plat/regs-serial.h>
  27 #include <mach/regs-gpio.h>
  28 #include <plat/regs-dma.h>
  29 #include <mach/regs-lcd.h>
  30 #include <mach/regs-sdi.h>
  31 #include <plat/regs-spi.h>
  32
  33 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
  34         [DMACH_XD0] = {
  35                 .name           = "xdreq0",
  36                 .channels[0]    = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  37         },
  38         [DMACH_XD1] = {
  39                 .name           = "xdreq1",
  40                 .channels[1]    = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  41         },
  42         [DMACH_SDI] = {
  43                 .name           = "sdi",
  44                 .channels[0]    = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  45                 .channels[1]    = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
  46                 .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  47                 .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  48         },
  49         [DMACH_SPI0] = {
  50                 .name           = "spi0",
  51                 .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  52         },
  53         [DMACH_SPI1] = {
  54                 .name           = "spi1",
  55                 .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  56         },
  57         [DMACH_UART0] = {
  58                 .name           = "uart0",
  59                 .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  60         },
  61         [DMACH_UART1] = {
  62                 .name           = "uart1",
  63                 .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  64         },
  65         [DMACH_UART2] = {
  66                 .name           = "uart2",
  67                 .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  68         },
  69         [DMACH_TIMER] = {
  70                 .name           = "timer",
  71                 .channels[0]    = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  72                 .channels[2]    = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  73                 .channels[3]    = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  74         },
  75         [DMACH_I2S_IN] = {
  76                 .name           = "i2s-sdi",
  77                 .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  78                 .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  79         },
  80         [DMACH_I2S_OUT] = {
  81                 .name           = "i2s-sdo",
  82                 .channels[0]    = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
  83                 .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  84         },
  85         [DMACH_PCM_IN] = {
  86                 .name           = "pcm-in",
  87                 .channels[0]    = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
  88                 .channels[2]    = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
  89         },
  90         [DMACH_PCM_OUT] = {
  91                 .name           = "pcm-out",
  92                 .channels[1]    = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
  93                 .channels[3]    = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
  94         },
  95         [DMACH_MIC_IN] = {
  96                 .name           = "mic-in",
  97                 .channels[2]    = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
  98                 .channels[3]    = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
  99         },
 100         [DMACH_USB_EP1] = {
 101                 .name           = "usb-ep1",
 102                 .channels[0]    = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
 103         },
 104         [DMACH_USB_EP2] = {
 105                 .name           = "usb-ep2",
 106                 .channels[1]    = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
 107         },
 108         [DMACH_USB_EP3] = {
 109                 .name           = "usb-ep3",
 110                 .channels[2]    = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
 111         },
 112         [DMACH_USB_EP4] = {
 113                 .name           = "usb-ep4",
 114                 .channels[3]    = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
 115         },
 116 };
 117
 118 static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
 119                                struct s3c24xx_dma_map *map)
 120 {
 121         chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
 122 }
 123
 124 static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
 125         .select         = s3c2440_dma_select,
 126         .dcon_mask      = 7 << 24,
 127         .map            = s3c2440_dma_mappings,
 128         .map_size       = ARRAY_SIZE(s3c2440_dma_mappings),
 129 };
 130
 131 static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
 132         .channels       = {
 133                 [DMACH_SDI]     = {
 134                         .list   = {
 135                                 [0]     = 3 | DMA_CH_VALID,
 136                                 [1]     = 2 | DMA_CH_VALID,
 137                                 [2]     = 1 | DMA_CH_VALID,
 138                                 [3]     = 0 | DMA_CH_VALID,
 139                         },
 140                 },
 141                 [DMACH_I2S_IN]  = {
 142                         .list   = {
 143                                 [0]     = 1 | DMA_CH_VALID,
 144                                 [1]     = 2 | DMA_CH_VALID,
 145                         },
 146                 },
 147                 [DMACH_I2S_OUT] = {
 148                         .list   = {
 149                                 [0]     = 2 | DMA_CH_VALID,
 150                                 [1]     = 1 | DMA_CH_VALID,
 151                         },
 152                 },
 153                 [DMACH_PCM_IN] = {
 154                         .list   = {
 155                                 [0]     = 2 | DMA_CH_VALID,
 156                                 [1]     = 1 | DMA_CH_VALID,
 157                         },
 158                 },
 159                 [DMACH_PCM_OUT] = {
 160                         .list   = {
 161                                 [0]     = 1 | DMA_CH_VALID,
 162                                 [1]     = 3 | DMA_CH_VALID,
 163                         },
 164                 },
 165                 [DMACH_MIC_IN] = {
 166                         .list   = {
 167                                 [0]     = 3 | DMA_CH_VALID,
 168                                 [1]     = 2 | DMA_CH_VALID,
 169                         },
 170                 },
 171         },
 172 };
 173
 174 static int __init s3c2440_dma_add(struct device *dev,
 175                                   struct subsys_interface *sif)
 176 {
 177         s3c2410_dma_init();
 178         s3c24xx_dma_order_set(&s3c2440_dma_order);
 179         return s3c24xx_dma_init_map(&s3c2440_dma_sel);
 180 }
 181
 182 static struct subsys_interface s3c2440_dma_interface = {
 183         .name           = "s3c2440_dma",
 184         .subsys         = &s3c2440_subsys,
 185         .add_dev        = s3c2440_dma_add,
 186 };
 187
 188 static int __init s3c2440_dma_init(void)
 189 {
 190         return subsys_interface_register(&s3c2440_dma_interface);
 191 }
 192
 193 arch_initcall(s3c2440_dma_init);
 194