1 /* linux/arch/arm/mach-s3c2443/dma.c
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2443 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
23 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-ac97.h>
29 #include <plat/regs-dma.h>
30 #include <mach/regs-lcd.h>
31 #include <mach/regs-sdi.h>
32 #include <plat/regs-iis.h>
33 #include <plat/regs-spi.h>
36 [0] = (x) | DMA_CH_VALID, \
37 [1] = (x) | DMA_CH_VALID, \
38 [2] = (x) | DMA_CH_VALID, \
39 [3] = (x) | DMA_CH_VALID, \
40 [4] = (x) | DMA_CH_VALID, \
41 [5] = (x) | DMA_CH_VALID, \
44 static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
47 .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
51 .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
53 [DMACH_SDI] = { /* only on S3C2443 */
55 .channels = MAP(S3C2443_DMAREQSEL_SDI),
59 .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
63 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
65 [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
67 .channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
69 [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
71 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
75 .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
79 .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
83 .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
87 .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
89 [DMACH_UART0_SRC2] = {
91 .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
93 [DMACH_UART1_SRC2] = {
95 .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
97 [DMACH_UART2_SRC2] = {
99 .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
101 [DMACH_UART3_SRC2] = {
103 .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
107 .channels = MAP(S3C2443_DMAREQSEL_TIMER),
111 .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
115 .channels = MAP(S3C2443_DMAREQSEL_I2STX),
119 .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
123 .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
127 .channels = MAP(S3C2443_DMAREQSEL_MICIN),
131 static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
132 struct s3c24xx_dma_map *map)
134 writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
135 chan->regs + S3C2443_DMA_DMAREQSEL);
138 static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
139 .select = s3c2443_dma_select,
141 .map = s3c2443_dma_mappings,
142 .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
145 static int __init s3c2443_dma_add(struct device *dev,
146 struct subsys_interface *sif)
148 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
149 return s3c24xx_dma_init_map(&s3c2443_dma_sel);
152 #ifdef CONFIG_CPU_S3C2416
153 /* S3C2416 DMA contains the same selection table as the S3C2443 */
154 static struct subsys_interface s3c2416_dma_interface = {
155 .name = "s3c2416_dma",
156 .subsys = &s3c2416_subsys,
157 .add_dev = s3c2443_dma_add,
160 static int __init s3c2416_dma_init(void)
162 return subsys_interface_register(&s3c2416_dma_interface);
165 arch_initcall(s3c2416_dma_init);
168 #ifdef CONFIG_CPU_S3C2443
169 static struct subsys_interface s3c2443_dma_interface = {
170 .name = "s3c2443_dma",
171 .subsys = &s3c2443_subsys,
172 .add_dev = s3c2443_dma_add,
175 static int __init s3c2443_dma_init(void)
177 return subsys_interface_register(&s3c2443_dma_interface);
180 arch_initcall(s3c2443_dma_init);