1 /* linux/arch/arm/mach-s3c2412/irq.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/device.h>
29 #include <mach/hardware.h>
32 #include <asm/mach/irq.h>
34 #include <mach/regs-irq.h>
35 #include <mach/regs-gpio.h>
41 #include "s3c2412-power.h"
43 #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
44 #define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
46 /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
47 * having them turn up in both the INT* and the EINT* registers. Whilst
48 * both show the status, they both now need to be acked when the IRQs
53 s3c2412_irq_mask(struct irq_data *data)
55 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
58 mask = __raw_readl(S3C2410_INTMSK);
59 __raw_writel(mask | bitval, S3C2410_INTMSK);
61 mask = __raw_readl(S3C2412_EINTMASK);
62 __raw_writel(mask | bitval, S3C2412_EINTMASK);
66 s3c2412_irq_ack(struct irq_data *data)
68 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
70 __raw_writel(bitval, S3C2412_EINTPEND);
71 __raw_writel(bitval, S3C2410_SRCPND);
72 __raw_writel(bitval, S3C2410_INTPND);
76 s3c2412_irq_maskack(struct irq_data *data)
78 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
81 mask = __raw_readl(S3C2410_INTMSK);
82 __raw_writel(mask|bitval, S3C2410_INTMSK);
84 mask = __raw_readl(S3C2412_EINTMASK);
85 __raw_writel(mask | bitval, S3C2412_EINTMASK);
87 __raw_writel(bitval, S3C2412_EINTPEND);
88 __raw_writel(bitval, S3C2410_SRCPND);
89 __raw_writel(bitval, S3C2410_INTPND);
93 s3c2412_irq_unmask(struct irq_data *data)
95 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
98 mask = __raw_readl(S3C2412_EINTMASK);
99 __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
101 mask = __raw_readl(S3C2410_INTMSK);
102 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
105 static struct irq_chip s3c2412_irq_eint0t4 = {
106 .irq_ack = s3c2412_irq_ack,
107 .irq_mask = s3c2412_irq_mask,
108 .irq_unmask = s3c2412_irq_unmask,
109 .irq_set_wake = s3c_irq_wake,
110 .irq_set_type = s3c_irqext_type,
113 #define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
115 /* CF and SDI sub interrupts */
117 static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
119 unsigned int subsrc, submsk;
121 subsrc = __raw_readl(S3C2410_SUBSRCPND);
122 submsk = __raw_readl(S3C2410_INTSUBMSK);
126 if (subsrc & INTBIT(IRQ_S3C2412_SDI))
127 generic_handle_irq(IRQ_S3C2412_SDI);
129 if (subsrc & INTBIT(IRQ_S3C2412_CF))
130 generic_handle_irq(IRQ_S3C2412_CF);
133 #define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
134 #define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
136 static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
138 s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
141 static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
143 s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
146 static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
148 s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
151 static struct irq_chip s3c2412_irq_cfsdi = {
152 .name = "s3c2412-cfsdi",
153 .irq_ack = s3c2412_irq_cfsdi_ack,
154 .irq_mask = s3c2412_irq_cfsdi_mask,
155 .irq_unmask = s3c2412_irq_cfsdi_unmask,
158 static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
160 unsigned long pwrcfg;
162 pwrcfg = __raw_readl(S3C2412_PWRCFG);
164 pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
166 pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
167 __raw_writel(pwrcfg, S3C2412_PWRCFG);
169 return s3c_irq_chip.irq_set_wake(data, state);
172 static struct irq_chip s3c2412_irq_rtc_chip;
174 static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
178 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
179 irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
181 set_irq_flags(irqno, IRQF_VALID);
184 /* add demux support for CF/SDI */
186 irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
188 for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
189 irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
191 set_irq_flags(irqno, IRQF_VALID);
194 /* change RTC IRQ's set wake method */
196 s3c2412_irq_rtc_chip = s3c_irq_chip;
197 s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
199 irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
204 static struct subsys_interface s3c2412_irq_interface = {
205 .name = "s3c2412_irq",
206 .subsys = &s3c2412_subsys,
207 .add_dev = s3c2412_irq_add,
210 static int s3c2412_irq_init(void)
212 return subsys_interface_register(&s3c2412_irq_interface);
215 arch_initcall(s3c2412_irq_init);