1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
21 #include <mach/hardware.h>
24 #include <mach/regs-sys.h>
25 #include <mach/regs-clock.h>
29 #include <plat/devs.h>
30 #include <plat/clock.h>
38 struct clk clk_27m = {
44 static int clk_48m_ctrl(struct clk *clk, int enable)
49 /* can't rely on clock lock, this register has other usages */
50 local_irq_save(flags);
52 val = __raw_readl(S3C64XX_OTHERS);
54 val |= S3C64XX_OTHERS_USBMASK;
56 val &= ~S3C64XX_OTHERS_USBMASK;
58 __raw_writel(val, S3C64XX_OTHERS);
59 local_irq_restore(flags);
64 struct clk clk_48m = {
68 .enable = clk_48m_ctrl,
71 static int inline s3c64xx_gate(void __iomem *reg,
75 unsigned int ctrlbit = clk->ctrlbit;
78 con = __raw_readl(reg);
85 __raw_writel(con, reg);
89 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
91 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
94 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
96 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
99 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
101 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
104 static struct clk init_clocks_disable[] = {
113 .enable = s3c64xx_pclk_ctrl,
114 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
119 .enable = s3c64xx_pclk_ctrl,
120 .ctrlbit = S3C_CLKCON_PCLK_IIC,
125 .enable = s3c64xx_pclk_ctrl,
126 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
131 .enable = s3c64xx_pclk_ctrl,
132 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
137 .enable = s3c64xx_pclk_ctrl,
138 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
143 .enable = s3c64xx_pclk_ctrl,
144 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
149 .enable = s3c64xx_sclk_ctrl,
150 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
155 .enable = s3c64xx_sclk_ctrl,
156 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
161 .enable = s3c64xx_sclk_ctrl,
162 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
167 .enable = s3c64xx_sclk_ctrl,
168 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
173 .enable = s3c64xx_sclk_ctrl,
174 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
179 .enable = s3c64xx_hclk_ctrl,
180 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
185 .enable = s3c64xx_hclk_ctrl,
186 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
190 static struct clk init_clocks[] = {
195 .enable = s3c64xx_hclk_ctrl,
196 .ctrlbit = S3C_CLKCON_HCLK_LCD,
201 .enable = s3c64xx_pclk_ctrl,
202 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
207 .enable = s3c64xx_hclk_ctrl,
208 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
213 .enable = s3c64xx_hclk_ctrl,
214 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
219 .enable = s3c64xx_hclk_ctrl,
220 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
225 .enable = s3c64xx_hclk_ctrl,
226 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
231 .enable = s3c64xx_pclk_ctrl,
232 .ctrlbit = S3C_CLKCON_PCLK_PWM,
237 .enable = s3c64xx_pclk_ctrl,
238 .ctrlbit = S3C_CLKCON_PCLK_UART0,
243 .enable = s3c64xx_pclk_ctrl,
244 .ctrlbit = S3C_CLKCON_PCLK_UART1,
249 .enable = s3c64xx_pclk_ctrl,
250 .ctrlbit = S3C_CLKCON_PCLK_UART2,
255 .enable = s3c64xx_pclk_ctrl,
256 .ctrlbit = S3C_CLKCON_PCLK_UART3,
261 .enable = s3c64xx_pclk_ctrl,
262 .ctrlbit = S3C_CLKCON_PCLK_RTC,
267 .ctrlbit = S3C_CLKCON_PCLK_WDT,
272 .ctrlbit = S3C_CLKCON_PCLK_AC97,
276 static struct clk *clks[] __initdata = {
284 void __init s3c64xx_register_clocks(void)
290 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
291 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
293 clkp = init_clocks_disable;
294 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
296 ret = s3c24xx_register_clock(clkp);
298 printk(KERN_ERR "Failed to register clock %s (%d)\n",
302 (clkp->enable)(clkp, 0);