1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
23 #include <mach/hardware.h>
26 #include <mach/regs-sys.h>
27 #include <mach/regs-clock.h>
31 #include <plat/devs.h>
32 #include <plat/cpu-freq.h>
33 #include <plat/clock.h>
34 #include <plat/clock-clksrc.h>
36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37 * ext_xtal_mux for want of an actual name from the manual.
40 static struct clk clk_ext_xtal_mux = {
45 #define clk_fin_apll clk_ext_xtal_mux
46 #define clk_fin_mpll clk_ext_xtal_mux
47 #define clk_fin_epll clk_ext_xtal_mux
49 #define clk_fout_mpll clk_mpll
50 #define clk_fout_epll clk_epll
58 struct clk clk_27m = {
64 static int clk_48m_ctrl(struct clk *clk, int enable)
69 /* can't rely on clock lock, this register has other usages */
70 local_irq_save(flags);
72 val = __raw_readl(S3C64XX_OTHERS);
74 val |= S3C64XX_OTHERS_USBMASK;
76 val &= ~S3C64XX_OTHERS_USBMASK;
78 __raw_writel(val, S3C64XX_OTHERS);
79 local_irq_restore(flags);
84 struct clk clk_48m = {
88 .enable = clk_48m_ctrl,
91 struct clk clk_xusbxti = {
97 static int inline s3c64xx_gate(void __iomem *reg,
101 unsigned int ctrlbit = clk->ctrlbit;
104 con = __raw_readl(reg);
111 __raw_writel(con, reg);
115 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
117 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
120 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
122 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
125 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
127 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
130 static struct clk init_clocks_disable[] = {
139 .enable = s3c64xx_pclk_ctrl,
140 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
145 .enable = s3c64xx_pclk_ctrl,
146 .ctrlbit = S3C_CLKCON_PCLK_IIC,
151 .enable = s3c64xx_pclk_ctrl,
152 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
157 .enable = s3c64xx_pclk_ctrl,
158 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
160 #ifdef CONFIG_CPU_S3C6410
162 .id = -1, /* There's only one IISv4 port */
164 .enable = s3c64xx_pclk_ctrl,
165 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
171 .enable = s3c64xx_pclk_ctrl,
172 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
177 .enable = s3c64xx_pclk_ctrl,
178 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
183 .enable = s3c64xx_sclk_ctrl,
184 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
189 .enable = s3c64xx_sclk_ctrl,
190 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
195 .enable = s3c64xx_sclk_ctrl,
196 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
201 .enable = s3c64xx_sclk_ctrl,
202 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
207 .enable = s3c64xx_sclk_ctrl,
208 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
213 .enable = s3c64xx_hclk_ctrl,
214 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
219 .enable = s3c64xx_hclk_ctrl,
220 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
224 static struct clk init_clocks[] = {
229 .enable = s3c64xx_hclk_ctrl,
230 .ctrlbit = S3C_CLKCON_HCLK_LCD,
235 .enable = s3c64xx_pclk_ctrl,
236 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
241 .enable = s3c64xx_hclk_ctrl,
242 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
247 .enable = s3c64xx_hclk_ctrl,
248 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
253 .enable = s3c64xx_hclk_ctrl,
254 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
259 .enable = s3c64xx_hclk_ctrl,
260 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
265 .enable = s3c64xx_hclk_ctrl,
266 .ctrlbit = S3C_CLKCON_HCLK_USB,
271 .enable = s3c64xx_pclk_ctrl,
272 .ctrlbit = S3C_CLKCON_PCLK_PWM,
277 .enable = s3c64xx_pclk_ctrl,
278 .ctrlbit = S3C_CLKCON_PCLK_UART0,
283 .enable = s3c64xx_pclk_ctrl,
284 .ctrlbit = S3C_CLKCON_PCLK_UART1,
289 .enable = s3c64xx_pclk_ctrl,
290 .ctrlbit = S3C_CLKCON_PCLK_UART2,
295 .enable = s3c64xx_pclk_ctrl,
296 .ctrlbit = S3C_CLKCON_PCLK_UART3,
301 .enable = s3c64xx_pclk_ctrl,
302 .ctrlbit = S3C_CLKCON_PCLK_RTC,
307 .ctrlbit = S3C_CLKCON_PCLK_WDT,
312 .ctrlbit = S3C_CLKCON_PCLK_AC97,
317 static struct clk clk_fout_apll = {
322 static struct clk *clk_src_apll_list[] = {
324 [1] = &clk_fout_apll,
327 static struct clksrc_sources clk_src_apll = {
328 .sources = clk_src_apll_list,
329 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
332 static struct clksrc_clk clk_mout_apll = {
337 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
338 .sources = &clk_src_apll,
341 static struct clk *clk_src_epll_list[] = {
343 [1] = &clk_fout_epll,
346 static struct clksrc_sources clk_src_epll = {
347 .sources = clk_src_epll_list,
348 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
351 static struct clksrc_clk clk_mout_epll = {
356 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
357 .sources = &clk_src_epll,
360 static struct clk *clk_src_mpll_list[] = {
362 [1] = &clk_fout_mpll,
365 static struct clksrc_sources clk_src_mpll = {
366 .sources = clk_src_mpll_list,
367 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
370 static struct clksrc_clk clk_mout_mpll = {
375 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
376 .sources = &clk_src_mpll,
379 static unsigned int armclk_mask;
381 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
383 unsigned long rate = clk_get_rate(clk->parent);
386 /* divisor mask starts at bit0, so no need to shift */
387 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
389 return rate / (clkdiv + 1);
392 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
395 unsigned long parent = clk_get_rate(clk->parent);
401 div = (parent / rate) - 1;
402 if (div > armclk_mask)
405 return parent / (div + 1);
408 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
410 unsigned long parent = clk_get_rate(clk->parent);
414 if (rate < parent / (armclk_mask + 1))
417 rate = clk_round_rate(clk, rate);
418 div = clk_get_rate(clk->parent) / rate;
420 val = __raw_readl(S3C_CLK_DIV0);
423 __raw_writel(val, S3C_CLK_DIV0);
429 static struct clk clk_arm = {
432 .parent = &clk_mout_apll.clk,
433 .ops = &(struct clk_ops) {
434 .get_rate = s3c64xx_clk_arm_get_rate,
435 .set_rate = s3c64xx_clk_arm_set_rate,
436 .round_rate = s3c64xx_clk_arm_round_rate,
440 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
442 unsigned long rate = clk_get_rate(clk->parent);
444 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
446 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
452 static struct clk_ops clk_dout_ops = {
453 .get_rate = s3c64xx_clk_doutmpll_get_rate,
456 static struct clk clk_dout_mpll = {
459 .parent = &clk_mout_mpll.clk,
460 .ops = &clk_dout_ops,
463 static struct clk *clkset_spi_mmc_list[] = {
470 static struct clksrc_sources clkset_spi_mmc = {
471 .sources = clkset_spi_mmc_list,
472 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
475 static struct clk *clkset_irda_list[] = {
482 static struct clksrc_sources clkset_irda = {
483 .sources = clkset_irda_list,
484 .nr_sources = ARRAY_SIZE(clkset_irda_list),
487 static struct clk *clkset_uart_list[] = {
494 static struct clksrc_sources clkset_uart = {
495 .sources = clkset_uart_list,
496 .nr_sources = ARRAY_SIZE(clkset_uart_list),
499 static struct clk *clkset_uhost_list[] = {
506 static struct clksrc_sources clkset_uhost = {
507 .sources = clkset_uhost_list,
508 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
511 /* The peripheral clocks are all controlled via clocksource followed
512 * by an optional divider and gate stage. We currently roll this into
513 * one clock which hides the intermediate clock from the mux.
515 * Note, the JPEG clock can only be an even divider...
517 * The scaler and LCD clocks depend on the S3C64XX version, and also
518 * have a common parent divisor so are not included here.
521 /* clocks that feed other parts of the clock source tree */
523 static struct clk clk_iis_cd0 = {
524 .name = "iis_cdclk0",
528 static struct clk clk_iis_cd1 = {
529 .name = "iis_cdclk1",
533 static struct clk clk_iisv4_cd = {
534 .name = "iis_cdclk_v4",
538 static struct clk clk_pcm_cd = {
543 static struct clk *clkset_audio0_list[] = {
544 [0] = &clk_mout_epll.clk,
545 [1] = &clk_dout_mpll,
551 static struct clksrc_sources clkset_audio0 = {
552 .sources = clkset_audio0_list,
553 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
556 static struct clk *clkset_audio1_list[] = {
557 [0] = &clk_mout_epll.clk,
558 [1] = &clk_dout_mpll,
564 static struct clksrc_sources clkset_audio1 = {
565 .sources = clkset_audio1_list,
566 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
569 static struct clk *clkset_audio2_list[] = {
570 [0] = &clk_mout_epll.clk,
571 [1] = &clk_dout_mpll,
577 static struct clksrc_sources clkset_audio2 = {
578 .sources = clkset_audio2_list,
579 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
582 static struct clk *clkset_camif_list[] = {
586 static struct clksrc_sources clkset_camif = {
587 .sources = clkset_camif_list,
588 .nr_sources = ARRAY_SIZE(clkset_camif_list),
591 static struct clksrc_clk clksrcs[] = {
596 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
597 .enable = s3c64xx_sclk_ctrl,
599 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
600 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
601 .sources = &clkset_spi_mmc,
606 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
607 .enable = s3c64xx_sclk_ctrl,
609 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
610 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
611 .sources = &clkset_spi_mmc,
616 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
617 .enable = s3c64xx_sclk_ctrl,
619 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
620 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
621 .sources = &clkset_spi_mmc,
624 .name = "usb-bus-host",
626 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
627 .enable = s3c64xx_sclk_ctrl,
629 .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
630 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
631 .sources = &clkset_uhost,
636 .ctrlbit = S3C_CLKCON_SCLK_UART,
637 .enable = s3c64xx_sclk_ctrl,
639 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
640 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
641 .sources = &clkset_uart,
643 /* Where does UCLK0 come from? */
647 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
648 .enable = s3c64xx_sclk_ctrl,
650 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
651 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
652 .sources = &clkset_spi_mmc,
657 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
658 .enable = s3c64xx_sclk_ctrl,
660 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
661 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
662 .sources = &clkset_spi_mmc,
667 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
668 .enable = s3c64xx_sclk_ctrl,
670 .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
671 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
672 .sources = &clkset_audio0,
677 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
678 .enable = s3c64xx_sclk_ctrl,
680 .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
681 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
682 .sources = &clkset_audio1,
686 .id = -1, /* There's only one IISv4 port */
687 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
688 .enable = s3c64xx_sclk_ctrl,
690 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
691 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
692 .sources = &clkset_audio2,
697 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
698 .enable = s3c64xx_sclk_ctrl,
700 .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
701 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
702 .sources = &clkset_irda,
707 .ctrlbit = S3C_CLKCON_SCLK_CAM,
708 .enable = s3c64xx_sclk_ctrl,
710 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
711 .reg_src = { .reg = NULL, .shift = 0, .size = 0 },
712 .sources = &clkset_camif,
716 /* Clock initialisation code */
718 static struct clksrc_clk *init_parents[] = {
724 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
726 void __init_or_cpufreq s3c6400_setup_clocks(void)
728 struct clk *xtal_clk;
740 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
742 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
743 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
745 xtal_clk = clk_get(NULL, "xtal");
746 BUG_ON(IS_ERR(xtal_clk));
748 xtal = clk_get_rate(xtal_clk);
751 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
753 /* For now assume the mux always selects the crystal */
754 clk_ext_xtal_mux.parent = xtal_clk;
756 epll = s3c6400_get_epll(xtal);
757 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
758 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
762 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
765 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
766 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
767 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
769 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
772 clk_fout_mpll.rate = mpll;
773 clk_fout_epll.rate = epll;
774 clk_fout_apll.rate = apll;
781 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
782 s3c_set_clksrc(init_parents[ptr], true);
784 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
785 s3c_set_clksrc(&clksrcs[ptr], true);
788 static struct clk *clks1[] __initdata = {
800 static struct clk *clks[] __initdata = {
810 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
811 * @xtal: The rate for the clock crystal feeding the PLLs.
812 * @armclk_divlimit: Divisor mask for ARMCLK.
814 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
815 * as ARMCLK as well as the necessary parent clocks.
817 * This call does not setup the clocks, which is left to the
818 * s3c6400_setup_clocks() call which may be needed by the cpufreq
819 * or resume code to re-set the clocks if the bootloader has changed
822 void __init s3c64xx_register_clocks(unsigned long xtal,
823 unsigned armclk_divlimit)
829 armclk_mask = armclk_divlimit;
831 s3c24xx_register_baseclocks(xtal);
832 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
834 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
836 clkp = init_clocks_disable;
837 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
839 ret = s3c24xx_register_clock(clkp);
841 printk(KERN_ERR "Failed to register clock %s (%d)\n",
845 (clkp->enable)(clkp, 0);
848 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
849 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));