1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
23 #include <mach/hardware.h>
26 #include <mach/regs-sys.h>
27 #include <mach/regs-clock.h>
30 #include <plat/devs.h>
31 #include <plat/cpu-freq.h>
32 #include <plat/clock.h>
33 #include <plat/clock-clksrc.h>
36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37 * ext_xtal_mux for want of an actual name from the manual.
40 static struct clk clk_ext_xtal_mux = {
44 #define clk_fin_apll clk_ext_xtal_mux
45 #define clk_fin_mpll clk_ext_xtal_mux
46 #define clk_fin_epll clk_ext_xtal_mux
48 #define clk_fout_mpll clk_mpll
49 #define clk_fout_epll clk_epll
56 struct clk clk_27m = {
61 static int clk_48m_ctrl(struct clk *clk, int enable)
66 /* can't rely on clock lock, this register has other usages */
67 local_irq_save(flags);
69 val = __raw_readl(S3C64XX_OTHERS);
71 val |= S3C64XX_OTHERS_USBMASK;
73 val &= ~S3C64XX_OTHERS_USBMASK;
75 __raw_writel(val, S3C64XX_OTHERS);
76 local_irq_restore(flags);
81 struct clk clk_48m = {
84 .enable = clk_48m_ctrl,
87 struct clk clk_xusbxti = {
92 static int inline s3c64xx_gate(void __iomem *reg,
96 unsigned int ctrlbit = clk->ctrlbit;
99 con = __raw_readl(reg);
106 __raw_writel(con, reg);
110 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
112 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
115 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
117 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
120 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
122 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
125 static struct clk init_clocks_off[] = {
132 .enable = s3c64xx_pclk_ctrl,
133 .ctrlbit = S3C_CLKCON_PCLK_RTC,
137 .enable = s3c64xx_pclk_ctrl,
138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
142 .enable = s3c64xx_pclk_ctrl,
143 .ctrlbit = S3C_CLKCON_PCLK_IIC,
146 .devname = "s3c2440-i2c.1",
148 .enable = s3c64xx_pclk_ctrl,
149 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
152 .devname = "samsung-i2s.0",
154 .enable = s3c64xx_pclk_ctrl,
155 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
158 .devname = "samsung-i2s.1",
160 .enable = s3c64xx_pclk_ctrl,
161 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
163 #ifdef CONFIG_CPU_S3C6410
166 .enable = s3c64xx_pclk_ctrl,
167 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
172 .enable = s3c64xx_pclk_ctrl,
173 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
176 .devname = "s3c64xx-spi.0",
178 .enable = s3c64xx_pclk_ctrl,
179 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
182 .devname = "s3c64xx-spi.1",
184 .enable = s3c64xx_pclk_ctrl,
185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
188 .devname = "s3c-sdhci.0",
190 .enable = s3c64xx_sclk_ctrl,
191 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
194 .devname = "s3c-sdhci.1",
196 .enable = s3c64xx_sclk_ctrl,
197 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
200 .devname = "s3c-sdhci.2",
202 .enable = s3c64xx_sclk_ctrl,
203 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
207 .enable = s3c64xx_hclk_ctrl,
208 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
212 .enable = s3c64xx_hclk_ctrl,
213 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
217 static struct clk clk_48m_spi0 = {
219 .devname = "s3c64xx-spi.0",
221 .enable = s3c64xx_sclk_ctrl,
222 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
225 static struct clk clk_48m_spi1 = {
227 .devname = "s3c64xx-spi.1",
229 .enable = s3c64xx_sclk_ctrl,
230 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
233 static struct clk init_clocks[] = {
237 .enable = s3c64xx_hclk_ctrl,
238 .ctrlbit = S3C_CLKCON_HCLK_LCD,
242 .enable = s3c64xx_pclk_ctrl,
243 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
247 .enable = s3c64xx_hclk_ctrl,
248 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
252 .enable = s3c64xx_hclk_ctrl,
253 .ctrlbit = S3C_CLKCON_HCLK_USB,
257 .enable = s3c64xx_pclk_ctrl,
258 .ctrlbit = S3C_CLKCON_PCLK_PWM,
261 .devname = "s3c6400-uart.0",
263 .enable = s3c64xx_pclk_ctrl,
264 .ctrlbit = S3C_CLKCON_PCLK_UART0,
267 .devname = "s3c6400-uart.1",
269 .enable = s3c64xx_pclk_ctrl,
270 .ctrlbit = S3C_CLKCON_PCLK_UART1,
273 .devname = "s3c6400-uart.2",
275 .enable = s3c64xx_pclk_ctrl,
276 .ctrlbit = S3C_CLKCON_PCLK_UART2,
279 .devname = "s3c6400-uart.3",
281 .enable = s3c64xx_pclk_ctrl,
282 .ctrlbit = S3C_CLKCON_PCLK_UART3,
286 .ctrlbit = S3C_CLKCON_PCLK_WDT,
290 .ctrlbit = S3C_CLKCON_PCLK_AC97,
294 .enable = s3c64xx_hclk_ctrl,
295 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
299 static struct clk clk_hsmmc0 = {
301 .devname = "s3c-sdhci.0",
303 .enable = s3c64xx_hclk_ctrl,
304 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
307 static struct clk clk_hsmmc1 = {
309 .devname = "s3c-sdhci.1",
311 .enable = s3c64xx_hclk_ctrl,
312 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
315 static struct clk clk_hsmmc2 = {
317 .devname = "s3c-sdhci.2",
319 .enable = s3c64xx_hclk_ctrl,
320 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
323 static struct clk clk_fout_apll = {
327 static struct clk *clk_src_apll_list[] = {
329 [1] = &clk_fout_apll,
332 static struct clksrc_sources clk_src_apll = {
333 .sources = clk_src_apll_list,
334 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
337 static struct clksrc_clk clk_mout_apll = {
341 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
342 .sources = &clk_src_apll,
345 static struct clk *clk_src_epll_list[] = {
347 [1] = &clk_fout_epll,
350 static struct clksrc_sources clk_src_epll = {
351 .sources = clk_src_epll_list,
352 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
355 static struct clksrc_clk clk_mout_epll = {
359 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
360 .sources = &clk_src_epll,
363 static struct clk *clk_src_mpll_list[] = {
365 [1] = &clk_fout_mpll,
368 static struct clksrc_sources clk_src_mpll = {
369 .sources = clk_src_mpll_list,
370 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
373 static struct clksrc_clk clk_mout_mpll = {
377 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
378 .sources = &clk_src_mpll,
381 static unsigned int armclk_mask;
383 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
385 unsigned long rate = clk_get_rate(clk->parent);
388 /* divisor mask starts at bit0, so no need to shift */
389 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
391 return rate / (clkdiv + 1);
394 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
397 unsigned long parent = clk_get_rate(clk->parent);
403 div = (parent / rate) - 1;
404 if (div > armclk_mask)
407 return parent / (div + 1);
410 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
412 unsigned long parent = clk_get_rate(clk->parent);
416 if (rate < parent / (armclk_mask + 1))
419 rate = clk_round_rate(clk, rate);
420 div = clk_get_rate(clk->parent) / rate;
422 val = __raw_readl(S3C_CLK_DIV0);
425 __raw_writel(val, S3C_CLK_DIV0);
431 static struct clk clk_arm = {
433 .parent = &clk_mout_apll.clk,
434 .ops = &(struct clk_ops) {
435 .get_rate = s3c64xx_clk_arm_get_rate,
436 .set_rate = s3c64xx_clk_arm_set_rate,
437 .round_rate = s3c64xx_clk_arm_round_rate,
441 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
443 unsigned long rate = clk_get_rate(clk->parent);
445 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
447 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
453 static struct clk_ops clk_dout_ops = {
454 .get_rate = s3c64xx_clk_doutmpll_get_rate,
457 static struct clk clk_dout_mpll = {
459 .parent = &clk_mout_mpll.clk,
460 .ops = &clk_dout_ops,
463 static struct clk *clkset_spi_mmc_list[] = {
470 static struct clksrc_sources clkset_spi_mmc = {
471 .sources = clkset_spi_mmc_list,
472 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
475 static struct clk *clkset_irda_list[] = {
482 static struct clksrc_sources clkset_irda = {
483 .sources = clkset_irda_list,
484 .nr_sources = ARRAY_SIZE(clkset_irda_list),
487 static struct clk *clkset_uart_list[] = {
494 static struct clksrc_sources clkset_uart = {
495 .sources = clkset_uart_list,
496 .nr_sources = ARRAY_SIZE(clkset_uart_list),
499 static struct clk *clkset_uhost_list[] = {
506 static struct clksrc_sources clkset_uhost = {
507 .sources = clkset_uhost_list,
508 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
511 /* The peripheral clocks are all controlled via clocksource followed
512 * by an optional divider and gate stage. We currently roll this into
513 * one clock which hides the intermediate clock from the mux.
515 * Note, the JPEG clock can only be an even divider...
517 * The scaler and LCD clocks depend on the S3C64XX version, and also
518 * have a common parent divisor so are not included here.
521 /* clocks that feed other parts of the clock source tree */
523 static struct clk clk_iis_cd0 = {
524 .name = "iis_cdclk0",
527 static struct clk clk_iis_cd1 = {
528 .name = "iis_cdclk1",
531 static struct clk clk_iisv4_cd = {
532 .name = "iis_cdclk_v4",
535 static struct clk clk_pcm_cd = {
539 static struct clk *clkset_audio0_list[] = {
540 [0] = &clk_mout_epll.clk,
541 [1] = &clk_dout_mpll,
547 static struct clksrc_sources clkset_audio0 = {
548 .sources = clkset_audio0_list,
549 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
552 static struct clk *clkset_audio1_list[] = {
553 [0] = &clk_mout_epll.clk,
554 [1] = &clk_dout_mpll,
560 static struct clksrc_sources clkset_audio1 = {
561 .sources = clkset_audio1_list,
562 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
565 static struct clk *clkset_audio2_list[] = {
566 [0] = &clk_mout_epll.clk,
567 [1] = &clk_dout_mpll,
573 static struct clksrc_sources clkset_audio2 = {
574 .sources = clkset_audio2_list,
575 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
578 static struct clk *clkset_camif_list[] = {
582 static struct clksrc_sources clkset_camif = {
583 .sources = clkset_camif_list,
584 .nr_sources = ARRAY_SIZE(clkset_camif_list),
587 static struct clksrc_clk clksrcs[] = {
590 .name = "usb-bus-host",
591 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
592 .enable = s3c64xx_sclk_ctrl,
594 .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
595 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
596 .sources = &clkset_uhost,
600 .devname = "samsung-i2s.0",
601 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
602 .enable = s3c64xx_sclk_ctrl,
604 .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
605 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
606 .sources = &clkset_audio0,
610 .devname = "samsung-i2s.1",
611 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
612 .enable = s3c64xx_sclk_ctrl,
614 .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
615 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
616 .sources = &clkset_audio1,
620 .devname = "samsung-i2s.2",
621 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
622 .enable = s3c64xx_sclk_ctrl,
624 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
625 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
626 .sources = &clkset_audio2,
630 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
631 .enable = s3c64xx_sclk_ctrl,
633 .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
634 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
635 .sources = &clkset_irda,
639 .ctrlbit = S3C_CLKCON_SCLK_CAM,
640 .enable = s3c64xx_sclk_ctrl,
642 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
643 .reg_src = { .reg = NULL, .shift = 0, .size = 0 },
644 .sources = &clkset_camif,
648 /* Where does UCLK0 come from? */
649 static struct clksrc_clk clk_sclk_uclk = {
652 .ctrlbit = S3C_CLKCON_SCLK_UART,
653 .enable = s3c64xx_sclk_ctrl,
655 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
656 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
657 .sources = &clkset_uart,
660 static struct clksrc_clk clk_sclk_mmc0 = {
663 .devname = "s3c-sdhci.0",
664 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
665 .enable = s3c64xx_sclk_ctrl,
667 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
668 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
669 .sources = &clkset_spi_mmc,
672 static struct clksrc_clk clk_sclk_mmc1 = {
675 .devname = "s3c-sdhci.1",
676 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
677 .enable = s3c64xx_sclk_ctrl,
679 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
680 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
681 .sources = &clkset_spi_mmc,
684 static struct clksrc_clk clk_sclk_mmc2 = {
687 .devname = "s3c-sdhci.2",
688 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
689 .enable = s3c64xx_sclk_ctrl,
691 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
692 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
693 .sources = &clkset_spi_mmc,
696 static struct clksrc_clk clk_sclk_spi0 = {
699 .devname = "s3c64xx-spi.0",
700 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
701 .enable = s3c64xx_sclk_ctrl,
703 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
704 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
705 .sources = &clkset_spi_mmc,
708 static struct clksrc_clk clk_sclk_spi1 = {
711 .devname = "s3c64xx-spi.1",
712 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
713 .enable = s3c64xx_sclk_ctrl,
715 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
716 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
717 .sources = &clkset_spi_mmc,
720 /* Clock initialisation code */
722 static struct clksrc_clk *init_parents[] = {
728 static struct clksrc_clk *clksrc_cdev[] = {
737 static struct clk *clk_cdev[] = {
745 static struct clk_lookup s3c64xx_clk_lookup[] = {
746 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
747 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
748 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
749 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
750 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
751 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
752 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
753 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
754 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
755 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
756 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
757 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
758 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
761 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
763 void __init_or_cpufreq s3c64xx_setup_clocks(void)
765 struct clk *xtal_clk;
777 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
779 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
780 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
782 xtal_clk = clk_get(NULL, "xtal");
783 BUG_ON(IS_ERR(xtal_clk));
785 xtal = clk_get_rate(xtal_clk);
788 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
790 /* For now assume the mux always selects the crystal */
791 clk_ext_xtal_mux.parent = xtal_clk;
793 epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
794 __raw_readl(S3C_EPLL_CON1));
795 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
796 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
800 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
803 if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
804 /* Synchronous mode */
805 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
807 /* Asynchronous mode */
808 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
810 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
811 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
813 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
816 clk_fout_mpll.rate = mpll;
817 clk_fout_epll.rate = epll;
818 clk_fout_apll.rate = apll;
825 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
826 s3c_set_clksrc(init_parents[ptr], true);
828 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
829 s3c_set_clksrc(&clksrcs[ptr], true);
832 static struct clk *clks1[] __initdata = {
844 static struct clk *clks[] __initdata = {
854 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
855 * @xtal: The rate for the clock crystal feeding the PLLs.
856 * @armclk_divlimit: Divisor mask for ARMCLK.
858 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
859 * as ARMCLK as well as the necessary parent clocks.
861 * This call does not setup the clocks, which is left to the
862 * s3c64xx_setup_clocks() call which may be needed by the cpufreq
863 * or resume code to re-set the clocks if the bootloader has changed
866 void __init s3c64xx_register_clocks(unsigned long xtal,
867 unsigned armclk_divlimit)
871 armclk_mask = armclk_divlimit;
873 s3c24xx_register_baseclocks(xtal);
874 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
876 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
878 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
879 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
881 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
882 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
883 s3c_disable_clocks(clk_cdev[cnt], 1);
885 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
886 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
887 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
888 s3c_register_clksrc(clksrc_cdev[cnt], 1);
889 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));