1 /* linux/arch/arm/plat-s3c64xx/dma.c
3 * Copyright 2009 Openmoko, Inc.
4 * Copyright 2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/dmapool.h>
19 #include <linux/sysdev.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
28 #include <mach/irqs.h>
30 #include <mach/regs-sys.h>
32 #include <asm/hardware/pl080.h>
34 /* dma channel state information */
37 struct sys_device sysdev;
40 struct s3c2410_dma_chan *channels;
44 /* pool to provide LLI buffers */
45 static struct dma_pool *dma_pool;
47 /* Debug configuration and code */
49 static unsigned char debug_show_buffs = 0;
51 static void dbg_showchan(struct s3c2410_dma_chan *chan)
53 pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
55 readl(chan->regs + PL080_CH_SRC_ADDR),
56 readl(chan->regs + PL080_CH_DST_ADDR),
57 readl(chan->regs + PL080_CH_LLI),
58 readl(chan->regs + PL080_CH_CONTROL),
59 readl(chan->regs + PL080S_CH_CONTROL2),
60 readl(chan->regs + PL080S_CH_CONFIG));
63 static void show_lli(struct pl080s_lli *lli)
65 pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
66 lli, lli->src_addr, lli->dst_addr, lli->next_lli,
67 lli->control0, lli->control1);
70 static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
72 struct s3c64xx_dma_buff *ptr;
73 struct s3c64xx_dma_buff *end;
75 pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
76 chan->number, chan->next, chan->curr, chan->end);
81 if (debug_show_buffs) {
82 for (; ptr != NULL; ptr = ptr->next) {
83 pr_debug("DMA%d: %08x ",
84 chan->number, ptr->lli_dma);
92 static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
94 struct s3c2410_dma_chan *chan;
95 unsigned int start, offs;
99 if (channel >= DMACH_PCM1_TX)
102 for (offs = 0; offs < 8; offs++) {
103 chan = &s3c2410_chans[start + offs];
111 s3c_dma_chan_map[channel] = chan;
115 int s3c2410_dma_config(unsigned int channel, int xferunit)
117 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
133 printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
139 EXPORT_SYMBOL(s3c2410_dma_config);
141 static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
142 struct pl080s_lli *lli,
143 dma_addr_t data, int size)
146 u32 control0, control1;
148 switch (chan->source) {
149 case S3C2410_DMASRC_HW:
150 src = chan->dev_addr;
152 control0 = PL080_CONTROL_SRC_AHB2;
153 control0 |= PL080_CONTROL_DST_INCR;
156 case S3C2410_DMASRC_MEM:
158 dst = chan->dev_addr;
159 control0 = PL080_CONTROL_DST_AHB2;
160 control0 |= PL080_CONTROL_SRC_INCR;
166 /* note, we do not currently setup any of the burst controls */
168 control1 = size >> chan->hw_width; /* size in no of xfers */
169 control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */
170 control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */
171 control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
172 control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
177 lli->control0 = control0;
178 lli->control1 = control1;
181 static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
182 struct pl080s_lli *lli)
184 void __iomem *regs = chan->regs;
186 pr_debug("%s: LLI %p => regs\n", __func__, lli);
189 writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
190 writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
191 writel(lli->next_lli, regs + PL080_CH_LLI);
192 writel(lli->control0, regs + PL080_CH_CONTROL);
193 writel(lli->control1, regs + PL080S_CH_CONTROL2);
196 static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
198 struct s3c64xx_dmac *dmac = chan->dmac;
204 pr_debug("%s: clearing interrupts\n", __func__);
206 /* clear interrupts */
207 writel(bit, dmac->regs + PL080_TC_CLEAR);
208 writel(bit, dmac->regs + PL080_ERR_CLEAR);
210 pr_debug("%s: starting channel\n", __func__);
212 config = readl(chan->regs + PL080S_CH_CONFIG);
213 config |= PL080_CONFIG_ENABLE;
215 pr_debug("%s: writing config %08x\n", __func__, config);
216 writel(config, chan->regs + PL080S_CH_CONFIG);
221 static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
226 pr_debug("%s: stopping channel\n", __func__);
230 config = readl(chan->regs + PL080S_CH_CONFIG);
231 config |= PL080_CONFIG_HALT;
232 writel(config, chan->regs + PL080S_CH_CONFIG);
236 config = readl(chan->regs + PL080S_CH_CONFIG);
237 pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
238 if (config & PL080_CONFIG_ACTIVE)
242 } while (--timeout > 0);
244 if (config & PL080_CONFIG_ACTIVE) {
245 printk(KERN_ERR "%s: channel still active\n", __func__);
249 config = readl(chan->regs + PL080S_CH_CONFIG);
250 config &= ~PL080_CONFIG_ENABLE;
251 writel(config, chan->regs + PL080S_CH_CONFIG);
256 static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
257 struct s3c64xx_dma_buff *buf,
258 enum s3c2410_dma_buffresult result)
260 if (chan->callback_fn != NULL)
261 (chan->callback_fn)(chan, buf->pw, 0, result);
264 static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
266 dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
270 static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
272 struct s3c64xx_dma_buff *buff, *next;
277 pr_debug("%s: flushing channel\n", __func__);
279 config = readl(chan->regs + PL080S_CH_CONFIG);
280 config &= ~PL080_CONFIG_ENABLE;
281 writel(config, chan->regs + PL080S_CH_CONFIG);
283 /* dump all the buffers associated with this channel */
285 for (buff = chan->curr; buff != NULL; buff = next) {
287 pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
289 s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
290 s3c64xx_dma_freebuff(buff);
293 chan->curr = chan->next = chan->end = NULL;
298 int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
300 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
307 case S3C2410_DMAOP_START:
308 return s3c64xx_dma_start(chan);
310 case S3C2410_DMAOP_STOP:
311 return s3c64xx_dma_stop(chan);
313 case S3C2410_DMAOP_FLUSH:
314 return s3c64xx_dma_flush(chan);
316 /* belive PAUSE/RESUME are no-ops */
317 case S3C2410_DMAOP_PAUSE:
318 case S3C2410_DMAOP_RESUME:
319 case S3C2410_DMAOP_STARTED:
320 case S3C2410_DMAOP_TIMEOUT:
326 EXPORT_SYMBOL(s3c2410_dma_ctrl);
332 int s3c2410_dma_enqueue(unsigned int channel, void *id,
333 dma_addr_t data, int size)
335 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
336 struct s3c64xx_dma_buff *next;
337 struct s3c64xx_dma_buff *buff;
338 struct pl080s_lli *lli;
346 buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_ATOMIC);
348 printk(KERN_ERR "%s: no memory for buffer\n", __func__);
352 lli = dma_pool_alloc(dma_pool, GFP_ATOMIC, &buff->lli_dma);
354 printk(KERN_ERR "%s: no memory for lli\n", __func__);
359 pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
360 __func__, buff, data, lli, (u32)buff->lli_dma, size);
365 s3c64xx_dma_fill_lli(chan, lli, data, size);
367 local_irq_save(flags);
369 if ((next = chan->next) != NULL) {
370 struct s3c64xx_dma_buff *end = chan->end;
371 struct pl080s_lli *endlli = end->lli;
373 pr_debug("enquing onto channel\n");
376 endlli->next_lli = buff->lli_dma;
378 if (chan->flags & S3C2410_DMAF_CIRCULAR) {
379 struct s3c64xx_dma_buff *curr = chan->curr;
380 lli->next_lli = curr->lli_dma;
383 if (next == chan->curr) {
384 writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
391 pr_debug("enquing onto empty channel\n");
397 s3c64xx_lli_to_regs(chan, lli);
400 local_irq_restore(flags);
413 EXPORT_SYMBOL(s3c2410_dma_enqueue);
416 int s3c2410_dma_devconfig(int channel,
417 enum s3c2410_dmasrc source,
418 unsigned long devaddr)
420 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
424 pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
425 __func__, channel, source, devaddr, chan);
431 peripheral = (chan->peripheral & 0xf);
432 chan->source = source;
433 chan->dev_addr = devaddr;
435 pr_debug("%s: peripheral %d\n", __func__, peripheral);
438 case S3C2410_DMASRC_HW:
439 config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
440 config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
442 case S3C2410_DMASRC_MEM:
443 config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
444 config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
447 printk(KERN_ERR "%s: bad source\n", __func__);
451 /* allow TC and ERR interrupts */
452 config |= PL080_CONFIG_TC_IRQ_MASK;
453 config |= PL080_CONFIG_ERR_IRQ_MASK;
455 pr_debug("%s: config %08x\n", __func__, config);
457 writel(config, chan->regs + PL080S_CH_CONFIG);
461 EXPORT_SYMBOL(s3c2410_dma_devconfig);
464 int s3c2410_dma_getposition(unsigned int channel,
465 dma_addr_t *src, dma_addr_t *dst)
467 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
474 *src = readl(chan->regs + PL080_CH_SRC_ADDR);
477 *dst = readl(chan->regs + PL080_CH_DST_ADDR);
481 EXPORT_SYMBOL(s3c2410_dma_getposition);
483 /* s3c2410_request_dma
485 * get control of an dma channel
488 int s3c2410_dma_request(unsigned int channel,
489 struct s3c2410_dma_client *client,
492 struct s3c2410_dma_chan *chan;
495 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
496 channel, client->name, dev);
498 local_irq_save(flags);
500 chan = s3c64xx_dma_map_channel(channel);
502 local_irq_restore(flags);
508 chan->client = client;
510 chan->peripheral = channel;
512 local_irq_restore(flags);
516 pr_debug("%s: channel initialised, %p\n", __func__, chan);
518 return chan->number | DMACH_LOW_LEVEL;
521 EXPORT_SYMBOL(s3c2410_dma_request);
525 * release the given channel back to the system, will stop and flush
526 * any outstanding transfers, and ensure the channel is ready for the
529 * Note, although a warning is currently printed if the freeing client
530 * info is not the same as the registrant's client info, the free is still
531 * allowed to go through.
534 int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
536 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
542 local_irq_save(flags);
544 if (chan->client != client) {
545 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
546 channel, chan->client, client);
549 /* sort out stopping and freeing the channel */
555 if (!(channel & DMACH_LOW_LEVEL))
556 s3c_dma_chan_map[channel] = NULL;
558 local_irq_restore(flags);
563 EXPORT_SYMBOL(s3c2410_dma_free);
565 static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
567 struct s3c64xx_dmac *dmac = pw;
568 struct s3c2410_dma_chan *chan;
569 enum s3c2410_dma_buffresult res;
574 tcstat = readl(dmac->regs + PL080_TC_STATUS);
575 errstat = readl(dmac->regs + PL080_ERR_STATUS);
577 for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
578 struct s3c64xx_dma_buff *buff;
580 if (!(errstat & bit) && !(tcstat & bit))
583 chan = dmac->channels + offs;
584 res = S3C2410_RES_ERR;
587 writel(bit, dmac->regs + PL080_TC_CLEAR);
588 res = S3C2410_RES_OK;
592 writel(bit, dmac->regs + PL080_ERR_CLEAR);
594 /* 'next' points to the buffer that is next to the
595 * currently active buffer.
596 * For CIRCULAR queues, 'next' will be same as 'curr'
597 * when 'end' is the active buffer.
600 while (buff && buff != chan->next
601 && buff->next != chan->next)
607 if (buff == chan->next)
610 s3c64xx_dma_bufffdone(chan, buff, res);
612 /* Free the node and update curr, if non-circular queue */
613 if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) {
614 chan->curr = buff->next;
615 s3c64xx_dma_freebuff(buff);
620 if (chan->next == chan->end) {
621 chan->next = chan->curr;
622 if (!(chan->flags & S3C2410_DMAF_CIRCULAR))
625 chan->next = buff->next;
632 static struct sysdev_class dma_sysclass = {
633 .name = "s3c64xx-dma",
636 static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
637 int irq, unsigned int base)
639 struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
640 struct s3c64xx_dmac *dmac;
643 void __iomem *regptr;
646 dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
648 printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
652 dmac->sysdev.id = chno / 8;
653 dmac->sysdev.cls = &dma_sysclass;
655 err = sysdev_register(&dmac->sysdev);
657 printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
661 regs = ioremap(base, 0x200);
663 printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
668 snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
670 dmac->clk = clk_get(NULL, clkname);
671 if (IS_ERR(dmac->clk)) {
672 printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
673 err = PTR_ERR(dmac->clk);
677 clk_enable(dmac->clk);
680 dmac->chanbase = chbase;
681 dmac->channels = chptr;
683 err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
685 printk(KERN_ERR "%s: failed to get irq\n", __func__);
689 regptr = regs + PL080_Cx_BASE(0);
691 for (ch = 0; ch < 8; ch++, chno++, chptr++) {
692 printk(KERN_INFO "%s: registering DMA %d (%p)\n",
693 __func__, chno, regptr);
695 chptr->bit = 1 << ch;
696 chptr->number = chno;
698 chptr->regs = regptr;
699 regptr += PL008_Cx_STRIDE;
702 /* for the moment, permanently enable the controller */
703 writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
705 printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
710 clk_disable(dmac->clk);
715 sysdev_unregister(&dmac->sysdev);
721 static int __init s3c64xx_dma_init(void)
725 printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
727 dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0);
729 printk(KERN_ERR "%s: failed to create pool\n", __func__);
733 ret = sysdev_class_register(&dma_sysclass);
735 printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
739 /* Set all DMA configuration to be DMA, not SDMA */
740 writel(0xffffff, S3C_SYSREG(0x110));
742 /* Register standard DMA controlers */
743 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
744 s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
749 arch_initcall(s3c64xx_dma_init);