1 /* linux/arch/arm/mach-s3c6400/include/mach/dma.h
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C6400 - DMA support
11 #ifndef __ASM_ARCH_DMA_H
12 #define __ASM_ARCH_DMA_H __FILE__
14 #define S3C_DMA_CHANNELS (16)
16 /* see mach-s3c2410/dma.h for notes on dma channel numbers */
18 /* Note, for the S3C64XX architecture we keep the DMACH_
19 * defines in the order they are allocated to [S]DMA0/[S]DMA1
20 * so that is easy to do DHACH_ -> DMA controller conversion
56 DMACH_SECURITY_RX, /* SDMA1 only */
57 DMACH_SECURITY_TX, /* SDMA1 only */
58 DMACH_MAX /* the end */
61 static __inline__ bool s3c_dma_has_circular(void)
66 #define S3C2410_DMAF_CIRCULAR (1 << 0)
70 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
72 struct s3c64xx_dma_buff;
74 /** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
75 * @next: Pointer to next buffer in queue or ring.
76 * @pw: Client provided identifier
77 * @lli: Pointer to hardware descriptor this buffer is associated with.
78 * @lli_dma: Hardare address of the descriptor.
80 struct s3c64xx_dma_buff {
81 struct s3c64xx_dma_buff *next;
84 struct pl080s_lli *lli;
90 struct s3c2410_dma_chan {
91 unsigned char number; /* number of this dma channel */
92 unsigned char in_use; /* channel allocated */
93 unsigned char bit; /* bit for enable/disable/etc */
94 unsigned char hw_width;
95 unsigned char peripheral;
98 enum s3c2410_dmasrc source;
103 struct s3c2410_dma_client *client;
104 struct s3c64xx_dmac *dmac; /* pointer to controller */
108 /* cdriver callbacks */
109 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
110 s3c2410_dma_opfn_t op_fn; /* channel op callback */
112 /* buffer list and information */
113 struct s3c64xx_dma_buff *curr; /* current dma buffer */
114 struct s3c64xx_dma_buff *next; /* next buffer to load */
115 struct s3c64xx_dma_buff *end; /* end of queue */
117 /* note, when channel is running in circular mode, curr is the
118 * first buffer enqueued, end is the last and curr is where the
119 * last buffer-done event is set-at. The buffers are not freed
120 * and the last buffer hardware descriptor points back to the
125 #include <plat/dma-core.h>
127 #endif /* __ASM_ARCH_IRQ_H */