1 /* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
3 * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
18 #include <linux/gpio.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/dm9000.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/serial_core.h>
25 #include <linux/types.h>
27 #include <asm/hardware/vic.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
33 #include <mach/regs-gpio.h>
34 #include <mach/regs-modem.h>
35 #include <mach/regs-srom.h>
39 #include <plat/devs.h>
41 #include <plat/nand.h>
42 #include <plat/regs-serial.h>
44 #include <plat/regs-fb-v4.h>
46 #include <video/platform_lcd.h>
50 #define UCON S3C2410_UCON_DEFAULT
51 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
52 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
54 static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
85 /* DM9000AEP 10/100 ethernet controller */
87 static struct resource mini6410_dm9k_resource[] = {
88 [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
89 [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
90 [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
91 | IORESOURCE_IRQ_HIGHLEVEL),
94 static struct dm9000_plat_data mini6410_dm9k_pdata = {
95 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
98 static struct platform_device mini6410_device_eth = {
101 .num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
102 .resource = mini6410_dm9k_resource,
104 .platform_data = &mini6410_dm9k_pdata,
108 static struct mtd_partition mini6410_nand_part[] = {
121 .size = MTDPART_SIZ_FULL,
122 .offset = SZ_1M + SZ_2M,
126 static struct s3c2410_nand_set mini6410_nand_sets[] = {
130 .nr_partitions = ARRAY_SIZE(mini6410_nand_part),
131 .partitions = mini6410_nand_part,
135 static struct s3c2410_platform_nand mini6410_nand_info = {
139 .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
140 .sets = mini6410_nand_sets,
143 static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
150 static struct fb_videomode mini6410_lcd_type0_timing = {
162 static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
169 static struct fb_videomode mini6410_lcd_type1_timing = {
181 static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
183 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
184 .vtiming = &mini6410_lcd_type0_timing,
185 .win[0] = &mini6410_lcd_type0_fb_win,
186 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
187 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
189 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
190 .vtiming = &mini6410_lcd_type1_timing,
191 .win[0] = &mini6410_lcd_type1_fb_win,
192 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
193 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
198 static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
202 gpio_direction_output(S3C64XX_GPE(0), 1);
204 gpio_direction_output(S3C64XX_GPE(0), 0);
207 static struct plat_lcd_data mini6410_lcd_power_data = {
208 .set_power = mini6410_lcd_power_set,
211 static struct platform_device mini6410_lcd_powerdev = {
212 .name = "platform-lcd",
213 .dev.parent = &s3c_device_fb.dev,
214 .dev.platform_data = &mini6410_lcd_power_data,
217 static struct platform_device *mini6410_devices[] __initdata = {
218 &mini6410_device_eth,
224 &mini6410_lcd_powerdev,
229 static void __init mini6410_map_io(void)
233 s3c64xx_init_io(NULL, 0);
234 s3c24xx_init_clocks(12000000);
235 s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
237 /* set the LCD type */
238 tmp = __raw_readl(S3C64XX_SPCON);
239 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
240 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
241 __raw_writel(tmp, S3C64XX_SPCON);
243 /* remove the LCD bypass */
244 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
245 tmp &= ~MIFPCON_LCD_BYPASS;
246 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
250 * mini6410_features string
252 * 0-9 LCD configuration
255 static char mini6410_features_str[12] __initdata = "0";
257 static int __init mini6410_features_setup(char *str)
260 strlcpy(mini6410_features_str, str,
261 sizeof(mini6410_features_str));
265 __setup("mini6410=", mini6410_features_setup);
267 #define FEATURE_SCREEN (1 << 0)
269 struct mini6410_features_t {
274 static void mini6410_parse_features(
275 struct mini6410_features_t *features,
276 const char *features_str)
278 const char *fp = features_str;
281 features->lcd_index = 0;
287 case '0'...'9': /* tft screen */
288 if (features->done & FEATURE_SCREEN) {
289 printk(KERN_INFO "MINI6410: '%c' ignored, "
290 "screen type already set\n", f);
293 if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
294 printk(KERN_INFO "MINI6410: '%c' out "
295 "of range LCD mode\n", f);
297 features->lcd_index = li;
300 features->done |= FEATURE_SCREEN;
306 static void __init mini6410_machine_init(void)
309 struct mini6410_features_t features = { 0 };
311 printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
312 mini6410_features_str);
314 /* Parse the feature string */
315 mini6410_parse_features(&features, mini6410_features_str);
317 printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
318 mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
319 mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
321 s3c_nand_set_platdata(&mini6410_nand_info);
322 s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
323 s3c24xx_ts_set_platdata(NULL);
325 /* configure nCS1 width to 16 bits */
327 cs1 = __raw_readl(S3C64XX_SROM_BW) &
328 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
329 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
330 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
331 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
332 S3C64XX_SROM_BW__NCS1__SHIFT;
333 __raw_writel(cs1, S3C64XX_SROM_BW);
335 /* set timing for nCS1 suitable for ethernet chip */
337 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
338 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
339 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
340 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
341 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
342 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
343 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
345 gpio_request(S3C64XX_GPF(15), "LCD power");
346 gpio_request(S3C64XX_GPE(0), "LCD power");
348 platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
351 MACHINE_START(MINI6410, "MINI6410")
352 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
353 .atag_offset = 0x100,
354 .init_irq = s3c6410_init_irq,
355 .handle_irq = vic_handle_irq,
356 .map_io = mini6410_map_io,
357 .init_machine = mini6410_machine_init,
358 .init_late = s3c64xx_init_late,
359 .timer = &s3c24xx_timer,
360 .restart = s3c64xx_restart,